US 12,645,458 B2Granted

Device, method and system for executing a tile load and expand instruction

AssigneeIntel Corporation

InventorsMenachem Adelman, Amit Gradstein, Simon Rubanovich, Barukh Ziv, Uri Sherman, Dana Rip, Shahar Mizrahi, Dan Baum, Rinat Rappoport, Nilesh Jain, Zeev Sperber, Gideon Stupp, Alexander Heinecke, Christopher Hughes, Evangelos Georganas

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Abstract

Techniques and mechanisms for processor circuitry to execute a load and expand instruction of an instruction set to generate decompressed matrix data. In an embodiment, the instruction comprises a source operand which indicates a location from which compressed matrix data, and corresponding metadata, are to be accessed. A destination operand of the instruction indicates a location which is to receive decompressed metadata, which is generated, during execution of the instruction, based on the compressed matrix data and the corresponding metadata. The metadata comprises compression mask information which identifies which elements of the matrix have been masked from the compressed matrix data. In another embodiment, the instruction further comprises a count operand which identifies a total number of the unmasked matrix elements which are represented in the compressed matrix data.

Claims14

Dependent claims

A processor comprising:

a decoder to decode a single instruction which is to comprise:
a first field to provide a first operand which indicates a destination location;
and
a second field to provide a second operand which indicates a source location;
execution circuitry coupled to the decoder, the execution circuitry to execute the decoded single instruction, comprising the execution circuitry to:
access the source location, based on the second operand, to load first data and metadata which corresponds to the first data, wherein the first data comprises a compressed version of a matrix;
execute a decompression operation, based on the first data and the metadata, to obtain second data which comprises a decompressed version of the matrix;
and
provide the second data to the destination location based on the first operand;
wherein:
the metadata is to comprise a bitmap which comprises bits each corresponding to a different respective location of the decompressed version of the matrix, wherein, for each of the bits, a respective value of the bit is to indicate whether a respective value at the corresponding location of the decompressed version of the matrix is to be equal to zero;
the single instruction is further to comprise a third field to provide a third operand which is to identify a total number of elements of the decompressed version of the matrix;
the execution circuitry is to execute the decompression operation further based on the third operand;
and the execution circuitry to execute the decompression operation comprises:
for each element of one or more elements of the compressed version of the matrix, the execution circuitry to:
determine a respective first location of the bitmap as corresponding to the element, wherein the execution circuitry is to determine the respective first location based on each of:
a first ordered sequence of multiple locations of the compressed version of the matrix;
a second ordered sequence of multiple locations of the bitmap;
and
a value of a respective bit at the respective first location;
determine a respective second location of the decompressed version of the matrix as corresponding to the element, wherein the execution circuitry is to determine the respective second location based on each of:
the respective first location of the bitmap;
and
a correspondence of the multiple locations of the bitmap each with a different respective location of multiple locations of the decompressed version of the matrix;
and
provide a value of the element at the respective second location.

23 more elements

A method at a processor, the method comprising:

translating a single instruction according to a first instruction set architecture (ISA) into one or more second instructions according to a second ISA, the single instruction comprising:
a first field comprising a first operand which indicates a destination location;
and
a second field comprising a second operand which indicates a source location;
decoding the one or more second instructions to generate a decoded one or more third instructions;
executing the decoded one or more third instructions with execution circuitry of the processor, comprising:
accessing the source location, based on the second operand, to load first data and metadata which corresponds to the first data, wherein the first data comprises a compressed version of a matrix;
executing a decompression operation, based on the first data and the metadata, to obtain second data which comprises a decompressed version of the matrix;
and
providing the second data to the destination location based on the first operand;
wherein:
the metadata comprises a bitmap which comprises bits each corresponding to a different respective location of the decompressed version of the matrix, wherein, for each of the bits, a respective value of the bit indicates whether a respective value at the corresponding location of the decompressed version of the matrix is to be equal to zero;
the single instruction further comprises a third field which provides a third operand which identifies a total number of elements of the decompressed version of the matrix;
executing the decompression operation is further based on the third operand;
and
executing the decompression operation comprises:
for each element of one or more elements of the compressed version of the matrix:
determining a respective first location of the bitmap as corresponding to the element, comprising determining the respective first location based on each of:
a first ordered sequence of multiple locations of the compressed version of the matrix;
a second ordered sequence of multiple locations of the bitmap;
and
a value of a respective bit at the respective first location;
determining a respective second location of the decompressed version of the matrix as corresponding to the element, comprising determining the respective second location based on each of:
the respective first location of the bitmap;
and
a correspondence of the multiple locations of the bitmap each with a different respective location of multiple locations of the decompressed version of the matrix;
and
providing a value of the element at the respective second location.

25 more elements

A non-transitory machine-readable medium storing one or more instructions which, when executed by a processor, causes the processor to perform a method, the method comprising:

decoding a single instruction which comprises:
a first field comprising a first operand which indicates a destination location;
and
a second field comprising a second operand which indicates a source location;
executing the decoded single instruction with execution circuitry of the processor, comprising:
accessing the source location, based on the second operand, to load first data and metadata which corresponds to the first data, wherein the first data comprises a compressed version of a matrix;
executing a decompression operation, based on the first data and the metadata, to obtain second data which comprises a decompressed version of the matrix;
and
providing the second data to the destination location based on the first operand;
wherein:
the metadata comprises a bitmap which comprises bits each corresponding to a different respective location of the decompressed version of the matrix, wherein, for each of the bits, a respective value of the bit indicates whether a respective value at the corresponding location of the decompressed version of the matrix is to be equal to zero;
the single instruction further comprises a third field which provides a third operand which identifies a total number of elements of the decompressed version of the matrix;
executing the decompression operation is further based on the third operand;
and
executing the decompression operation comprises:
for each element of one or more elements of the compressed version of the matrix:
determining a respective first location of the bitmap as corresponding to the element, comprising determining the respective first location based on each of:
a first ordered sequence of multiple locations of the compressed version of the matrix;
a second ordered sequence of multiple locations of the bitmap;
and
a value of a respective bit at the respective first location;
determining a respective second location of the decompressed version of the matrix as corresponding to the element, comprising determining the respective second location based on each of:
the respective first location of the bitmap;
and
a correspondence of the multiple locations of the bitmap each with a different respective location of multiple locations of the decompressed version of the matrix;
and
providing a value of the element at the respective second location.

24 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/841,558Filed 15 Jun 2022
Published: US 2023/0409326 A121 Dec 2023
Granted: 2 Jun 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

G06F 9/30038
Instructions to perform operations on packed data, e.g. vector, tile or matrix operations: using a mask
G06F 9/30145
Arrangements for executing machine instructions, e.g. instruction decode: instruction analysis, e.g. decoding, instruction word fields
G06F 9/30032
To perform operations on data operands: movement instructions, e.g. move, shift, rotate, shuffle
G06F 9/30043
To perform operations on memory: lOAD or STORE instructions; Clear instruction