Data transfer for vectors in neural networks

A data processing apparatus, comprising:

• a mode determining circuit configured to determine a transfer mode of a data transfer instruction when a decoded processing instruction is the data transfer instruction, wherein the decoded processing instruction includes an operation domain;
• an address determining circuit configured to
• determine first source data addresses and first destination data addresses of a plurality of first data points as well as second source data addresses and second destination data addresses of a plurality of second data points in an operation domain of the data transfer instruction, when the transfer mode of the data transfer instruction is a multi-vector transfer mode,
• wherein the operation domain of the data transfer instruction includes a source data base address, a destination data base address, a single point data size, a single point data number, an offset vector base address, an offset size, an offset stride, and a destination base address stride;
• wherein the offset size is a width of an offset address corresponding to each of the plurality of the first data points and is equal to the single point data size, and
• wherein the offset stride is an offset between a first address of the first source data addresses and a first address of the second source data addresses;
• and
• obtain the second source data addresses by applying the offset stride to the first source data addresses;
• a first storage circuit configured to obtain first vector data by storing the first data points read from the first source data addresses to the first destination data addresses;
• and
• a second storage circuit configured to obtain second vector data by storing the second data points read from the second source data addresses to the second destination data addresses, wherein
• the first source data addresses and the second source data addresses are discrete data addresses, and the first destination data addresses and the second destination data addresses are consecutive data addresses.

An electronic device that includes a data processing apparatus, the data processing apparatus comprising:

• a mode determining circuit configured to determine a transfer mode of a data transfer instruction when a decoded processing instruction is the data transfer instruction, wherein the decoded processing instruction includes an operation domain;
• an address determining circuit configured to
• determine first source data addresses and first destination data addresses of a plurality of first data points as well as second source data addresses and second destination data addresses of a plurality of second data points in an operation domain of the data transfer instruction, when the transfer mode of the data transfer instruction is a multi-vector transfer mode,
• wherein the operation domain of the data transfer instruction includes a source data base address, a destination data base address, a single point data size, a single point data number, an offset vector base address, an offset size, an offset stride, and a destination base address stride,
• wherein the offset size is a width of an offset address corresponding to each of the plurality of the first data points and is equal to the single point data size, and
• wherein the offset stride is an offset between a first address of the first source data addresses and a first address of the second source data addresses;
• and
• obtain the second source data addresses by applying the offset stride to the first source data addresses;
• a first storage circuit configured to obtain first vector data by storing the first data points read from the first source data addresses to the first destination data addresses;
• and
• a second storage circuit configured to obtain second vector data by storing the second data points read from the second source data addresses to the second destination data addresses, wherein
• the first source data addresses and the second source data addresses are discrete data addresses, and the first destination data addresses and the second destination data addresses are consecutive data addresses.