Static power reduction in caches using deterministic naps
AssigneeTexas Instruments Incorporated
InventorsOluleye Olorode, Mehrdad Nourani
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Abstract
Disclosed embodiments relate to a dNap architecture that accurately transitions cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.
Claims20
A memory system comprising:
- a memory including cache lines;
- and
- decoding and logic circuitry coupled to the memory, wherein the decoding and logic circuitry is configured to:
- receive a memory access request,
- decode an address associated with the memory access request to determine a first subset of the cache lines to which the memory access request is directed,
- cause transition of the first subset of the cache lines from a low power state to an operating state, and
- determine that the memory access request is associated with a hit in a second subset of the cache lines, the second subset of the cache lines being a subset of the first subset of the cache lines, and in response thereto, transition a third subset of the cache lines from the operating state to the low power state, the third subset of the cache lines being a subset of the first subset of cache lines and mutually exclusive of the second subset of the cache lines.
A memory system, comprising:
- a tag memory and a data memory having cache lines, wherein the data memory is configured to be accessed to retrieve data in a plurality of addressable locations of the data memory in response to cache access requests, each cache access request including a request address;
- decoder circuitry configured to receive bits related to the requested addresses, decode the bits, and output a set of decoded output signals;
- and
- logic circuitry configured to receive the sets of decoded output signals from the decoder circuitry and to output respective power enable signals, including a first power enable signal,
- wherein a first group of cache lines of the data memory is controllable to be in one of an operating state and a lower power state in response to the first power enable signal, and
- wherein the first power enable signal is generated based on multiple power enable signals, which is at least a subset of all of the power enable signals output by the logic circuitry.
Dependencies are inferred from the claim text.