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AssigneeQUALCOMM Incorporated
InventorsRajesh Arimilli, Bharat Kumar Rangarajan, Raashid Moin Shaikh, Venkata Biswanath Devarasetty, Ramakrishna Gottimukkula, Rohit Singh
Estimating the term…
A processor cluster includes a first processor core electrically coupled directly to a power rail and a second processor core coupled to the power rail through power switches. The first processor core consumes power due to leakage currents during idle states. The second processor core is electrically decoupled from the power rail during idle states by the power switches, but the power switches cause a performance degradation. A scheduler assigns tasks to the first processor core rather than the second processor core to maximize performance and minimize power consumption due to leakage currents. Some tasks may indicate that they can be executed on a lower-performance core type, which may be the core type of the second processor core, but those tasks may be assigned to the first processor core while the second processor core is turned off.
An integrated circuit (IC) comprising:
A processor cluster comprising:
A method in a processor cluster comprising a first processor core electrically coupled to a first power rail, a first power switch electrically coupled to the first power rail, and a second processor core electrically coupled to the first power switch and configured to execute a first task, the method comprising:
Dependencies are inferred from the claim text.