Display panel and display apparatus

A display panel, comprising:

• a first base substrate, comprising:
• common voltage lines, a common electrode, a second electrode of a thin film transistor, and a pixel electrode that are located in different film layers;
• wherein the common electrode is electrically connected with one of the common voltage lines through a common electrode via hole, and the pixel electrode is connected with the second electrode of the thin film transistor through a pixel via hole;
• a second base substrate opposite to the first base substrate;
• and
• a plurality of spacers between the first base substrate and the second base substrate;
• wherein the first base substrate is provided with a plurality of pixel units, each of the plurality of pixel units comprises a plurality of sub-pixels, and each of the plurality of sub-pixels is correspondingly provided with the common electrode via hole and the pixel via hole;
• the plurality of sub-pixels comprise a first sub-pixel and a second sub-pixel adjacent to each other along a first direction;
• wherein, in the first direction, an orthographic projection of at least one spacer of the plurality of spacers on the first base substrate is between an orthographic projection of the common electrode via hole corresponding to the first sub-pixel on the first base substrate and an orthographic projection of the pixel via hole corresponding to the second sub-pixel on the first base substrate;
• the common voltage lines are in the same one layer as a gate electrode of the thin film transistor, the second electrode of the thin film transistor is on a side of the gate electrode of the thin film transistor facing away from the first base substrate, the common electrode is on a side of the second electrode of the thin film transistor facing away from the first base substrate, and the pixel electrode is on a side of the common electrode facing away from the first base substrate;
• the display panel further comprises:
• an insulating layer between the gate electrode of the thin film transistor and the second electrode of the thin film transistor, a planarization layer between the second electrode of the thin film transistor and the common voltage lines, a first passivation layer between the common electrode and the pixel electrode, a first conductive connection electrode that is in the same layer as the pixel electrode, and a second conductive connection electrode that is in the same layer as the second electrode of the thin film transistor;
• the second conductive connection electrode is in contact with the common voltage line through a first via hole;
• wherein the first via hole penetrates the insulating layer;
• and
• the first conductive connection electrode is in contact with the second conductive connection electrode through a second via hole, and the first conductive connection electrode is in contact with the common electrode through a third via hole;
• wherein the common electrode via hole penetrates from a surface of the first passivation layer facing away from the first base substrate to the second conductive connection electrode and the common electrode, and the second via hole is a portion of the common electrode via hole penetrating to the second conductive connection electrode, and the third via hole is a portion of the common electrode via hole penetrating to the common electrode.