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US 12,645,118 B2Granted
Display panel having clock signal wires partially overlapping with gate drivers on array and related display device
AssigneeTcl China Star Optoelectronics Technology Co., Ltd.
InventorMeng Hu
Life of this patent
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Abstract
A display panel and a display device are provided. The display panel includes a substrate, clock signal wires disposed on the substrate, and a GOA circuit. The GOA circuit includes cascaded GOA units. The GOA circuit and the clock signal wire are arranged on different layers. The GOA units are correspondingly connected to the clock signal wires via holes. A positive projection of the plurality of clock signal wires on the substrate overlaps a positive projection of the GOA circuit on the substrate.
Claims9
A display panel, comprising:
- a substrate;
- a plurality of clock signal wires, comprising one or more first clock signal wires and one or more second clock signal wires, disposed on the substrate and arranged in a first direction;
- a gate driver on array (GOA) circuit, comprising a plurality of cascaded GOA units arranged in a second direction perpendicular to the first direction, wherein the GOA circuit and the clock signal wires are arranged on different layers, and the GOA units are correspondingly connected to the clock signal wires via one or more holes;
- wherein the display panel further comprises an insulating layer disposed between the clock signal wires and the GOA circuit, and the holes are disposed in the insulating layer, wherein in a plane perpendicular to a plane in which the substrate lies, an extension direction of the hole corresponding to each first clock signal wire and an extension direction of the hole corresponding to each second clock signal wire are not parallel;
- wherein a positive projection of the plurality of clock signal wires on the substrate overlaps a positive projection of the GOA circuit on the substrate;
- wherein the first clock signal wire intersects the plurality of GOA units on different layers;
- a positive projection of the second clock signal wire on the substrate is interlaced with the positive projection of the GOA unit on the substrate;
- and
- wherein the extension direction of the hole which the first clock signal wire corresponds to is parallel to a thickness direction of the insulating layer, and an aperture of the hole which the second clock signal wire corresponds to is greater than an aperture of the hole which the first clock signal wire corresponds to.
6 more elements
A display device comprising:
- a timing controller;
- and
- a display panel, comprising:
- a substrate;
- a plurality of clock signal wires, comprising one or more first clock signal wires and one or more second clock signal wires, disposed on the substrate and arranged in a first direction;
- a gate driver on array (GOA) circuit, comprising a plurality of cascaded GOA units arranged in a second direction perpendicular to the first direction, wherein the GOA circuit and the clock signal wires are arranged on different layers, and the GOA units are correspondingly connected to the clock signal wires via one or more holes;
- wherein the display panel further comprises an insulating layer disposed between the clock signal wires and the GOA circuit, the holes are disposed in the insulating layer, and an extension direction of the hole which each first clock signal wire corresponds to is parallel to a thickness direction of the insulating layer, wherein in a plane perpendicular to a plane in which the substrate lies, the extension direction of the hole corresponding to each first clock signal wire and an extension direction of the hole corresponding to each second clock signal wire are not parallel, and wherein a pitch between the second clock signal wire and its corresponding GOA unit along the extension direction of the hole corresponding to the second clock signal wire is greater than a pitch between the first clock signal wire and its corresponding GOA unit along the extension direction of the hole corresponding to the first clock signal wire;
- wherein a positive projection of the plurality of clock signal wires on the substrate overlaps a positive projection of the GOA circuit on the substrate;
- and
- wherein each of the holes which the second clock signal wires correspond to comprises a plurality of sub-holes;
- each second clock signal wire is connected to the corresponding GOA unit through the plurality of sub-holes;
- and an aperture of each of the holes which the first clock signal wires corresponds to is the same as an aperture of the sub-hole.
9 more elements
Dependencies are inferred from the claim text.