Real-time debug in low-power devices
AssigneeSTMicroelectronics International N.V.
InventorsGourav Garg, Balwinder Singh Soni, Dinesh Chandra Joshi, Sumit Kumar Singhal
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Abstract
According to an embodiment, a method for debugging a low-power domain in a multi-power domain device is disclosed. The method includes mapping a critical signal of the low-power domain to a latch circuit of a register bank; capturing, by the latch circuit, transitions of the critical signal in registers of the register bank; observing, by a core circuit in a switchable power domain of the multi-power domain device, registers of the register bank; and determining a fault corresponding to the critical signal based on a value of the registers of the register bank.
Claims20
A method for debugging a low-power domain in a multi-power domain device, the method comprising:
- mapping a critical signal of the low-power domain to a latch circuit of a register bank;
- capturing, by the latch circuit, transitions of the critical signal in registers of the register bank;
- observing, by a core circuit in a switchable power domain of the multi-power domain device, registers of the register bank;
- and
- determining a fault corresponding to the critical signal based on a value of the registers of the register bank.
A method for debugging a low-power domain in a multi-power domain device, the method comprising:
- mapping a critical signal of the low-power domain to a latch circuit of a register bank;
- capturing, by the latch circuit, transitions of the critical signal in registers of the register bank;
- mapping, by a low-power system capture circuit in the low-power domain, data stored in the registers of the register bank to an externally accessible pad;
- and
- determining a fault corresponding to the critical signal based on a value of the externally accessible pad.
A multi-power domain device comprising a low-power domain, the low-power domain comprising:
- a register bank configured to store captured values associated with transitions of critical signals of the low-power domain during a debug mode;
- and
- a low-power system capture circuit configured to map data stored in registers of the register bank to a first externally accessible pad to determine faults within the low-power domain.
Dependencies are inferred from the claim text.