Package substrate with embedded device, and manufacturing method therefor

A manufacturing method for a package substrate with an embedded device, comprising:

• manufacturing a third circuit layer and a target on an upper surface of a temporary carrier plate, and laminating a third dielectric layer on the third circuit layer and the target;
• placing a device to be embedded on the third dielectric layer and covering the device to be embedded with a second dielectric layer, wherein a pin of the device to be embedded is arranged opposite to the third dielectric layer;
• laminating a second copper foil on an upper surface of the second dielectric layer, and manufacturing a second circuit layer, a second copper pillar, and a third copper pillar through the second copper foil;
• laminating a first dielectric layer on the second circuit layer, the second copper pillar, and the third copper pillar, laminating a first copper foil on an upper surface of the first dielectric layer, and removing the temporary carrier plate;
• laminating a fourth dielectric layer on a lower surface of the third circuit layer, and laminating a fourth copper foil on a lower surface of the fourth dielectric layer;
• and
• manufacturing a fourth circuit layer and a fourth copper pillar through the fourth copper foil, and manufacturing a first circuit layer and a first copper pillar through the first copper foil;
• or,
• manufacturing a target on a temporary carrier plate, and laminating a third dielectric layer on the target;
• placing a device to be embedded on the third dielectric layer and covering the device to be embedded with a second dielectric layer, wherein a pin of the device to be embedded is attached to the third dielectric layer;
• laminating a second copper foil on an upper surface of the second dielectric layer, and manufacturing a third circuit layer through the second copper foil;
• covering the third circuit layer with a first dielectric layer, laminating a first copper foil on an upper surface of the first dielectric layer, and removing the temporary carrier plate to expose a lower surface of the third dielectric layer;
• manufacturing a second circuit layer, a second copper pillar and a third copper pillar on the lower surface of the third dielectric layer;
• laminating the fourth dielectric layer on the second circuit layer, the second copper pillar and the third copper pillar, and laminating a fourth copper foil on a lower surface of the fourth dielectric layer;
• and
• manufacturing a first circuit layer and a first copper pillar through the fourth copper foil, and manufacturing a fourth circuit layer and a fourth copper pillar through the first copper foil;
• wherein the manufacturing a second circuit layer, a second copper pillar and a third copper pillar through the second copper foil comprises:
• manufacturing a second via hole and a third via hole, wherein the second via hole penetrates through the third dielectric layer and the second dielectric layer;
• manufacturing a second metal seed layer on the second copper foil, the second via hole and the third via hole;
• and
• manufacturing the second circuit layer, the second copper pillar and the third copper pillar on the second metal seed layer.