Reduction of middle-of-line resistance and capacitance
AssigneeInternational Business Machines Corporation
InventorsBrent A. Anderson, Nicholas Anthony Lanzillo, Albert M. Chu, Ruilong Xie, Lawrence A. Clevenger, Reinaldo Vega
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Abstract
A semiconductor structure includes a plurality of vertical transport field effect transistors, and an interconnect structure connected to one of respective source/drain regions of at least two vertical transport field effect transistors of the plurality of vertical transport field effect transistors and respective gate regions of the at least two vertical transport field effect transistors. The interconnect structure comprises a damascene portion, and a subtractive portion disposed on the damascene portion.
Claims20
A semiconductor structure, comprising:
- a plurality of vertical transport field effect transistors;
- and
- an interconnect structure connected to one of respective source/drain regions of at least two vertical transport field effect transistors of the plurality of vertical transport field effect transistors and respective gate regions of the at least two vertical transport field effect transistors, wherein the interconnect structure comprises:
- a damascene portion;
- and
- a subtractive portion disposed on a top surface of the damascene portion.
A semiconductor structure, comprising:
- a plurality of vertical semiconductor channel regions;
- a plurality of source/drain regions, wherein respective ones of the plurality of source/drain regions are disposed on top of respective ones the plurality of vertical semiconductor channel regions;
- and
- an interconnect structure connected to the respective ones of the plurality of source/drain regions, wherein the interconnect structure comprises:
- a damascene portion;
- and
- a subtractive portion disposed on a top surface of the damascene portion.
Dependencies are inferred from the claim text.