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US 12,642,077 B2Granted
Integrated circuit chip with backside power delivery and multiple types of backside to frontside vias
AssigneeInternational Business Machines Corporation
InventorsBrent A. Anderson, Nicholas Anthony Lanzillo, Ruilong Xie, Lawrence A. Clevenger, Albert M. Chu, Nicholas Alexander Polomoff
Life of this patent
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Abstract
A semiconductor device that includes a first via connecting a backside of the semiconductor device to a frontside of the semiconductor device, and a second via connecting the backside of the semiconductor device to the frontside of the semiconductor device. The first via and the second via are directly connected to at least one different wiring level on the frontside or the backside.
Claims18
A semiconductor device comprising:
- a first plurality of vias connecting a backside metallization level of the semiconductor device to a frontside metallization level of the semiconductor device;
- and
- a second plurality of vias connecting the backside metallization level of the semiconductor device to the frontside metallization level of the semiconductor device,
- wherein the first plurality of vias are connected to a first single wiring level and the second plurality of vias are connected to a second single wiring level, and wherein the first plurality of vias and the second plurality of vias extend continuously from the backside metallization level to the frontside metallization level.
1 more element
A semiconductor device comprising:
- a first set of vias connecting a backside metallization level of the semiconductor device to a frontside metallization level of the semiconductor device;
- and
- a second set of vias connecting the backside metallization level of the semiconductor device to the frontside metallization level of the semiconductor device,
- wherein at least one via of the first set of vias and at least one via of the second set of vias are directly connected to at least one different wiring level on the frontside metallization level or the backside metallization level, and the first set of vias are connected to a first single wiring level and the second set of vias are connected to a second single wiring level, and wherein the first plurality of vias and the second plurality of vias extend continuously from the backside metallization level to the frontside metallization level.
1 more element
Dependencies are inferred from the claim text.