Semiconductor device

A semiconductor device comprising:

• a substrate;
• transistors on the substrate;
• a first interlayer insulating layer on the transistors;
• and
• a first metal layer in the first interlayer insulating layer,
• wherein the first metal layer comprises a first interconnection line in an upper portion of the first interlayer insulating layer,
• wherein the first interconnection line comprises:
• a first barrier pattern;
• a first liner on an inner surface of the first barrier pattern;
• a first conductive pattern on the first liner;
• and
• a first capping pattern on a top surface of the first conductive pattern and on a top surface of the first liner,
• wherein the first liner includes a ruthenium cobalt (RuCo) compound,
• wherein the top surface of the first liner is at a lower level than a top surface of the first barrier pattern, and
• wherein a ratio of a first height between an uppermost point of the top surface of the first conductive pattern and a lowermost point of the top surface of the first liner to a height of the first interconnection line ranges from 1% to 5%.

A semiconductor device comprising:

• a substrate comprising an active region;
• a device isolation layer forming an active pattern on the active region;
• a source pattern and a drain pattern on the active pattern;
• a channel pattern connected to the source pattern and the drain pattern on the active pattern, the channel pattern comprising a first semiconductor pattern, a second semiconductor pattern and a third semiconductor pattern sequentially stacked and spaced apart from each other;
• a gate electrode intersecting the channel pattern and extending in a first direction;
• a gate insulating layer between the channel pattern and the gate electrode;
• a gate spacer on a sidewall of the gate electrode;
• a gate capping pattern on a top surface of the gate electrode;
• a first interlayer insulating layer on the gate capping pattern;
• an active contact penetrating the first interlayer insulating layer and connected to the source pattern and the drain pattern;
• a gate contact penetrating the first interlayer insulating layer and the gate capping pattern and connected to the gate electrode;
• a second interlayer insulating layer on the first interlayer insulating layer;
• a first metal layer provided in the second interlayer insulating layer, the first metal layer comprising a first interconnection line electrically connected to at least one of the active contact or the gate contact;
• a third interlayer insulating layer on the second interlayer insulating layer;
• and
• a second metal layer in the third interlayer insulating layer,
• wherein the second metal layer comprises a second interconnection line electrically connected to the first metal layer,
• wherein the first interconnection line comprises:
• a first barrier pattern;
• a first liner on the first barrier pattern;
• and
• a first conductive pattern on the first liner,
• wherein the second interconnection line comprises:
• a second barrier pattern;
• a second liner on the second barrier pattern;
• and
• a second conductive pattern on the second liner,
• wherein the first liner includes a ruthenium cobalt (RuCo) compound, and the second liner includes cobalt (Co), and
• wherein a first height between an uppermost point of a top surface of the first conductive pattern and a lowermost point of a top surface of the first liner is less than a second height between an uppermost point of a top surface of the second conductive pattern and a lowermost point of a top surface of the second liner.