Transistor cells including a deep via lined with a dielectric material
AssigneeIntel Corporation
InventorsPatrick Morrow, Mauro J. Kobrinsky, Rishabh Mehandru
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AssigneeIntel Corporation
InventorsPatrick Morrow, Mauro J. Kobrinsky, Rishabh Mehandru
Estimating the term…
A transistor cell including a deep via that is at least partially lined with a dielectric material. The deep via may extend down to a substrate over which the transistor is disposed. The deep via may be directly connected to a terminal of the transistor, such as the source or drain, to interconnect the transistor with an interconnect metallization level disposed in the substrate under the transistor, or on at opposite side of the substrate as the transistor. Parasitic capacitance associated with the close proximity of the deep via metallization to one or more terminals of the transistor may be reduced by lining at least a portion of the deep via sidewall with dielectric material, partially necking the deep via metallization in a region adjacent to the transistor.
A method of fabricating a transistor structure, the method comprising:
A method of fabricating an integrated circuit (IC) structure, the method comprising:
A method of fabricating a field effect transistor (FET) structure, the method comprising:
Dependencies are inferred from the claim text.