Methods for patterning substrates to adjust voltage properties

A method of adjusting a threshold voltage in a field-effect-transistor (FET) device, comprising:

• performing a first deposition process to deposit a first diffusion barrier layer over a gate dielectric layer in a first region, a second region, a third region, and a fourth region of a semiconductor structure;
• performing a first patterning process to remove a portion of the deposited first diffusion barrier layer in the first region;
• performing a second deposition process to deposit a second diffusion barrier layer over the gate dielectric layer in the first region and the first diffusion barrier layer in the second region, the third region, and the fourth region;
• performing a second patterning process to partially remove a portion of the deposited second diffusion barrier layer in the first region and the second region;
• performing a third deposition process to deposit a third diffusion barrier layer over the gate dielectric layer in the first region, the first diffusion barrier layer in the second region, and the second diffusion barrier layer in the third region and the fourth region;
• performing a third patterning process to partially remove a portion of the deposited third diffusion barrier layer in the first region, the second region, and the third region;
• performing a dipole layer deposition process to deposit a dipole layer over the gate dielectric layer in the first region, the first diffusion barrier layer in the second region, the second diffusion barrier layer in the third region, and the third diffusion barrier layer;
• and
• performing an annealing process to drive dipole dopants from the dipole layer into the gate dielectric layer.