Fin-type field effect transistor with independently biasable supplementary gate and method

A structure comprising:

• a first semiconductor fin on a semiconductor substrate and having a top surface and opposing sidewalls;
• an isolation region on the semiconductor substrate positioned laterally adjacent to the opposing sidewalls;
• an isolation structure and a first gate structure on the isolation region and positioned laterally adjacent to the opposing sidewalls, respectively, wherein the first gate structure further extends over the top surface of the first semiconductor fin and abuts the isolation structure;
• a supplementary gate structure integrated into the isolation structure and including:
• a conductor layer within an opening extending into the isolation structure;
• and a portion of the isolation structure positioned laterally between the first semiconductor fin and the conductor layer, wherein the conductor layer further fills a via that extends through the substrate and the isolation region to the opening;
• and
• a dielectric cap within the opening on the conductor layer.

A method comprising:

• forming a first semiconductor fin on a semiconductor substrate and having a top surface and opposing sidewalls;
• forming an isolation region on the semiconductor substrate positioned laterally adjacent to the opposing sidewalls;
• forming, on the isolation region, an isolation structure and a first gate structure positioned laterally adjacent to the opposing sidewalls, respectively, wherein the first gate structure extends over the top surface of the first semiconductor fin and abuts the isolation structure;
• and
• forming a supplementary gate structure integrated into the isolation structure, wherein the supplementary gate structure includes:
• a conductor layer within an opening extending through the isolation structure;
• and a portion of the isolation structure positioned laterally between the first semiconductor fin and the conductor layer,
• wherein the first semiconductor fin includes a channel region, and
• wherein the first gate structure and the supplementary gate structure are adjacent to the opposing sidewalls of the first semiconductor fin at the channel region.