Semiconductor device with recessed gate and method for fabricating the same
AssigneeNanya Technology Corporation
InventorYing-Cheng Chuang
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Abstract
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a recessed gate dielectric layer inwardly positioned in the substrate and including a U-shaped cross-sectional profile; a recessed gate bottom conductive layer positioned on the recessed gate dielectric layer and including a valley-shaped cross-sectional profile, resulting in a first valley; a recessed gate top conductive layer conformally positioned on the first valley of the recessed gate bottom conductive layer; and a recessed gate capping layer positioned on the recessed gate top conductive layer.
Claims12
A semiconductor device, comprising:
- a substrate;
- a recessed gate dielectric layer inwardly positioned in the substrate and comprising a U-shaped cross-sectional profile, wherein two top ends of the recessed gate dielectric layer are extended in opposite directions and are aligned on a top surface of the substrate;
- a recessed gate bottom conductive layer positioned on the recessed gate dielectric layer and comprising a valley-shaped cross-sectional profile, resulting in a first valley;
- a recessed gate top conductive layer conformally positioned on the first valley of the recessed gate bottom conductive layer;
- and
- a recessed gate capping layer positioned on the recessed gate top conductive layer;
- wherein a width between the top ends of the recessed gate dielectric layer, a width of the recessed gate bottom conductive layer, a width of the recessed gate top conductive layer, and a width of the recess gate capping layer are equal;
- wherein a top surface of the recessed gate bottom conductive layer is at a vertical level higher than a top surface of the substrate;
- wherein a bottom surface of the recessed gate top conductive layer is at a vertical level lower than the top surface of the substrate;
- wherein a bottom portion of the recessed gate capping layer is at a vertical level lower than the top surface of the substrate, wherein the bottom portion of the recessed gate capping layer has a reversed-triangular cross-sectional profile.
A semiconductor device, comprising:
- a substrate comprising a first peripheral region and a second peripheral region, wherein the substrate further has a plurality of gate recesses indented from a top surface of the substrate at the first peripheral region only;
- a plurality of recessed gates respectively formed at the gate recesses and comprising:
- a recessed gate dielectric layer inwardly positioned in the first peripheral region and comprising a U-shaped cross-sectional profile;
- a recessed gate bottom conductive layer positioned on the recessed gate dielectric layer and comprising a valley-shaped cross-sectional profile, resulting in a first valley;
- a recessed gate top conductive layer conformally positioned on the first valley of the recessed gate bottom conductive layer;
- and
- a recessed gate capping layer positioned on the recessed gate top conductive layer;
- and
- a peripheral gate structure positioned on the second peripheral region, wherein the peripheral gate structure is in contact with the top surface of the substrate at the second peripheral region thereof;
- wherein an element density of the first peripheral region is greater than an element density of the second peripheral region;
- wherein a width of the recessed gate is less than a width of the peripheral gate structure.
Dependencies are inferred from the claim text.