US 12,641,850 B2 · Lattice stack for internal spacer fabrication

Abstract

Techniques are provided herein to form gate-all-around (GAA) semiconductor devices, such as those having a stacked transistor configuration. In one example case, two different semiconductor devices may both be GAA transistors each having any number of nanoribbons extending in the same (e.g., horizontal) direction where one device is located vertically above the other device. An internal spacer structure extends between the nanoribbons of both devices along the vertical direction, where the spacer structure includes one or more rib features between the two devices. A gate structure that includes one or more gate dielectric layers and one or more gate electrode layers may be formed around the nanoribbons of both devices, in some cases. In other cases, a split-gate configuration is used where upper and lower gate structures are separated by an isolation structure. Forksheet transistors and other GAA configurations may be formed using the techniques as well.

Claims20

Dependent claims

An integrated circuit comprising:

a first semiconductor body extending in a first direction between a first source region and a first drain region and a second semiconductor body extending in the first direction between a second source region and a second drain region, the first semiconductor body spaced vertically from the second semiconductor body in a second direction orthogonal to the first direction;
a dielectric spacer structure that extends between the first semiconductor body and the second semiconductor body in the second direction, wherein the dielectric spacer structure includes a plurality of rib features between the first semiconductor body and the second semiconductor body, wherein the plurality of rib features includes at least one rib feature having a first recess above the at least one rib feature along the second direction and a second recess below the at least one rib feature along the second direction;
and
a gate structure around one or both the first semiconductor body and the second semiconductor body.

1 more element

An electronic device, comprising:

a chip package comprising one or more dies, at least one of the one or more dies comprising
a semiconductor device having a first plurality of semiconductor nanoribbons extending in a first direction between a first source region and a first drain region and a second plurality of semiconductor nanoribbons extending in the first direction between a second source region and a second drain region, the first plurality of semiconductor nanoribbons spaced vertically from the second plurality of semiconductor nanoribbons in a second direction orthogonal to the first direction;
a dielectric spacer structure that extends between the first plurality of semiconductor nanoribbons and the second plurality of semiconductor nanoribbons in the second direction, wherein the dielectric spacer structure includes a plurality of rib features between the first plurality of semiconductor nanoribbons and the second plurality of semiconductor nanoribbons, wherein the plurality of rib features includes at least one rib feature having a first recess above the at least one rib feature along the second direction and a second recess below the at least one rib feature along the second direction;
and
a gate structure around both the first plurality of semiconductor nanoribbons and the second plurality of semiconductor nanoribbons.

2 more elements

Dependencies are inferred from the claim text.

Lattice stack for internal spacer fabrication

Life of this patent

Lattice stack for internal spacer fabrication

Life of this patent

Abstract

Claims20