Semiconductor device and method of manufacturing thereof

A complementary metal-oxide-semiconductor (CMOS) device comprising:

• a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) formed on a semiconductor substrate,
• the PFET and the NFET each comprise:
• a fin extending along a first direction over a substrate;
• a gate structure extending in a second direction overlying the fin,
• wherein the gate structure comprises:
• a gate dielectric layer overlying the fin;
• a gate electrode overlying the gate dielectric layer;
• and
• insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction,
• wherein a portion of the fin under the gate structure is a channel region;
• a source/drain region in the fin in a region adjacent the gate structure,
• wherein the source/drain region consists essentially of Ge or SiGe and a first dopant;
• a stressor layer below the source/drain region,
• wherein the stressor layer comprises GeSn or SiGeSn containing about 1019 atoms cm−3 or less of a dopant;
• and
• a strain relaxed buffer layer between the stressor layer and the semiconductor substrate,
• wherein the PFET and NFET are spaced apart from each other with an insulating layer therebetween.

A semiconductor device comprising:

• a fin extending along a first direction over a semiconductor substrate;
• a gate structure extending in a second direction overlying a channel region of the fin,
• wherein the gate structure comprises:
• a gate dielectric layer overlying the channel region of the fin;
• a gate electrode overlying the gate dielectric layer;
• and
• a source/drain region in the fin in a region adjacent the channel region of the fin, a stressor layer disposed below the source/drain region;
• and
• a strain relaxed buffer layer disposed between stressor layer and the semiconductor substrate,
• wherein the stressor layer is at least partially embedded in the strain relaxed buffer layer.