Device scaling by isolation enhancement

A method, comprising:

• forming a channel region of a transistor, the channel region including one or more semiconductor nanostructures;
• forming one or more dielectric layers on the channel region;
• forming a gate electrode at least partially surrounding the one or more semiconductor nanostructures;
• and on the one or more dielectric layers, the one or more dielectric layers including a high-k dielectric layer between the channel region and the gate electrode, and the high-k dielectric layer is on a first sidewall of the gate electrode and a second sidewall of the gate electrode opposite to the first sidewall;
• forming a first spacer abutting the high-k dielectric layer by removing a portion of a first spacer layer, the high-k dielectric layer extending laterally between the first spacer and the first sidewall of the gate electrode;
• forming a second spacer abutting the high-k dielectric layer by removing a portion of the second spacer layer, the high-k dielectric layer extending laterally between the second spacer and the second sidewall of the gate electrode;
• forming one or more recesses by removing the portion of the first spacer layer and by removing the portion of the second spacer layer exposing respective surfaces of one or more source/drain regions, an interlayer dielectric layer, and a first liner layer between the one or more source/drain regions and the interlayer dielectric layer;
• forming a dielectric liner layer in and partially filling the one or more recesses, on the one or more source/drain regions, and on the first sidewall and the second sidewall of the gate electrode, wherein the second liner layer has a dielectric constant less than a dielectric constant of the high-k dielectric layer of the one or more dielectric layers;
• and
• forming a second dielectric layer on the second liner layer filling respective remaining portions of the one or more recesses.

A method, comprising:

• forming a plurality of semiconductor nanostructures of a plurality of channel regions spaced apart from one another over a semiconductor substrate;
• forming a gate electrode on the plurality of semiconductor nanostructures of the plurality of channel regions, the gate electrode having a first sidewall and a second sidewall opposite to the first sidewall;
• forming a first dielectric layer between the gate electrode and each of the plurality of channel regions;
• forming a first spacer by removing a portion of a first spacer layer adjacent the first sidewall of the gate electrode and a second spacer by removing a portion of a second spacer layer adjacent the second sidewall of the gate electrode, the first dielectric layer extending laterally between first spacer and the first sidewall of the gate electrode, and the first dielectric layer extending laterally between the second spacer and the second sidewall of the gate electrode;
• forming a plurality of recesses by removing the portion of the first spacer layer and by removing the portion of the second spacer layer exposing respective surfaces of a plurality of source/drain regions, an interlayer dielectric layer, and a first liner layer between the plurality of source/drain regions and the interlayer dielectric layer;
• forming a second liner layer in the plurality of recesses, on the plurality of source/drain regions, and on the first sidewall and the second sidewall of the gate electrode, and wherein the second dielectric liner layer having a dielectric constant less than the dielectric constant of the first dielectric layer;
• and
• forming a second dielectric layer on the second liner layer and in the plurality of recesses.