US 12,641,800 B2Granted

Capacitor structure and semiconductor device including the same

AssigneeSamsung Electronics Co., Ltd.

InventorsJungmin Park, Intak Jeon, Hanjin Lim, Hyungsuk Jung

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Abstract

A capacitor structure includes a first lower conductive pattern, a first capacitor, a first upper conductive pattern, a second lower conductive pattern, a second capacitor and a second upper conductive pattern. The first capacitor includes first lower electrodes, first upper electrodes and first dielectric structures. Each of the first dielectric structures are disposed between one of the first lower electrodes and a corresponding one of the first upper electrodes. The first upper conductive pattern is formed on and is electrically connected to the first upper electrodes. The second lower conductive pattern is spaced apart from the first lower conductive pattern disposed on the substrate. The second capacitor includes second lower electrodes, second upper electrodes and second dielectric structures. The second upper conductive pattern is formed on and is electrically connected to the second upper electrodes. The first and second conductive patterns are electrically insulated from each other.

Claims20

Dependent claims

A capacitor structure, comprising:

a first lower conductive pattern disposed on a substrate;
a first capacitor including:
first lower electrodes spaced apart from each other on the first lower conductive pattern in a horizontal direction that is substantially parallel to an upper surface of the substrate, the first lower electrodes being electrically connected to the first lower conductive pattern;
first upper electrodes disposed in a space between the first lower electrodes and further disposed in a space adjacent to one of the first lower electrodes that is disposed at a first end portion;
and
first dielectric structures, each disposed between one of the first lower electrodes and a corresponding one of the first upper electrodes;
a first upper conductive pattern disposed on and electrically connected to the first upper electrodes;
a second lower conductive pattern disposed on the substrate, the second lower conductive pattern being spaced apart from the first lower conductive pattern;
a second capacitor including:
second lower electrodes spaced apart from each other on the second lower conductive pattern in the horizontal direction, the second lower electrodes being electrically connected to the second lower conductive pattern;
second upper electrodes disposed in a space between the second lower electrodes and further disposed in a space adjacent to one of the second lower electrodes that is disposed at a first end portion;
and
second dielectric structures each being disposed between one of the second lower electrodes and a corresponding one of the second upper electrodes;
and
a second upper conductive pattern disposed on and electrically connected to the second upper electrodes,
wherein the first and second conductive patterns are electrically insulated from each other.

13 more elements

A capacitor structure, comprising:

a first lower conductive pattern disposed on a substrate;
a first capacitor including:
first lower electrodes spaced apart from each other on the first lower conductive pattern in a horizontal direction that is substantially parallel to an upper surface of the substrate, the first lower electrodes being electrically connected to the first lower conductive pattern;
first upper electrodes disposed in a space between the first lower electrodes and further disposed in a space adjacent to one of the first lower electrodes that is disposed at a first end portion;
and
first dielectric structures each being disposed between one of the first lower electrodes and a corresponding one of the first upper electrodes;
a first upper conductive pattern disposed on and electrically connected to the first upper electrodes;
a second lower conductive pattern disposed on the substrate, the second lower conductive pattern being spaced apart from the first lower conductive pattern;
a second capacitor including:
second lower electrodes spaced apart from each other on the second lower conductive pattern in the horizontal direction, the second lower electrodes being electrically connected to the second lower conductive pattern;
second upper electrodes disposed in a space between the second lower electrodes and further disposed in a space adjacent to one of the second lower electrodes that is disposed at a first end portion;
and
second dielectric structures each being disposed between one of the second lower electrodes and a corresponding one of the second upper electrodes;
and
a second upper conductive pattern disposed on and electrically connected to the second upper electrodes,
wherein each of the first dielectric structures includes a third dielectric pattern extending in a vertical direction that is substantially perpendicular to the upper surface of the substrate, a second dielectric pattern disposed on a sidewall of the third dielectric pattern, and a first dielectric pattern disposed on an outer sidewall of the second dielectric pattern and contacting sidewalls of the first lower electrode and the first upper electrode, and
wherein each of the second dielectric structures includes a fifth dielectric pattern extending in the vertical direction, and a fourth dielectric pattern disposed on a sidewall of the fifth dielectric pattern and contacting sidewalls of the second lower electrode and the second upper electrode.

14 more elements

A capacitor structure, comprising:

a first lower conductive pattern disposed on a substrate;
a first capacitor including:
first lower electrodes spaced apart from each other on the first lower conductive pattern in a horizontal direction that is substantially parallel to an upper surface of the substrate, the first lower electrodes being electrically connected to the first lower conductive pattern;
first upper electrodes disposed in a space between the first lower electrodes and further disposed in a space adjacent to one of the first lower electrodes that is disposed at a first end portion;
and
first dielectric structures each being disposed between one of the first lower electrodes and a corresponding one of the first upper electrodes;
a first upper conductive pattern disposed on and electrically connected to the first upper electrodes;
a second lower conductive pattern disposed on the substrate, the second lower conductive pattern being spaced apart from the first lower conductive pattern;
a second capacitor including:
second lower electrodes spaced apart from each other on the second lower conductive pattern in the horizontal direction, the second lower electrodes being electrically connected to the second lower conductive pattern;
second upper electrodes disposed in a space between the second lower electrodes and further disposed in a space adjacent to one of the second lower electrodes that is disposed at a first end portion;
and
second dielectric structures each being disposed between one of the second lower electrodes and a corresponding one of the second upper electrodes;
and
a second upper conductive pattern disposed on and electrically connected to the second upper electrodes,
wherein each of the first dielectric structures includes a first dielectric pattern extending in a vertical direction that is substantially perpendicular to the upper surface of the substrate, and at least one second dielectric pattern disposed on a sidewall of the first dielectric pattern, and
wherein each of the second dielectric structures includes a third dielectric pattern extending in the vertical direction, and at least one fourth dielectric pattern disposed on a sidewall of the fifth dielectric pattern, and
wherein a number of the second dielectric pattern is different from a number of the fourth dielectric patterns.

15 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/461,408Filed 5 Sep 2023
Priority: KR 10-2022-011806319 Sep 2022
Published: US 2024/0105765 A128 Mar 2024
Granted: 26 May 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10D 1/043
Of capacitors having no potential barriers: using patterning processes to form electrode extensions, e.g. etching
H10B 12/03
For one transistor one-capacitor [1T-1C] memory cells: making the capacitor or connections thereto
H10B 12/033
Making the capacitor or connections thereto: the capacitor extending over the transistor
H10B 12/0335
The capacitor extending over the transistor: making a connection between the transistor and the capacitor, e.g. plug