Memory device and method for controlling verification voltage of memory device

A memory device, comprising:

• a first memory sector;
• a controller, configured to determine a bit count of data bits verified in one verification cycle to be K according to electrical characteristics of the first memory sector, wherein K is a positive integer;
• and
• a charge pump circuit, coupled to the controller, and configured to transmit a verification voltage to the first memory sector;
• wherein:
• the controller is configured to control the charge pump circuit to start detecting the verification voltage and start pulling up the verification voltage at a beginning time point of a present verification cycle;
• the controller is further configured to control the charge pump circuit to stop pulling up the verification voltage at a verification time point of the present verification cycle in response to the verification voltage reaching a predetermined level;
• and
• K data bits written into the memory device are verified based on the verification voltage after the verification time point of the present verification cycle.