Field effect transistor with top-protected gate electrode and methods for forming the same

A semiconductor structure comprising:

• a first field effect transistor;
• a second field effect transistor, wherein the first field effect transistor comprises:
• a first source region and a first drain region embedded in a first portion of a semiconductor substrate;
• a first gate dielectric and a first gate electrode;
• a first dielectric gate liner laterally surrounding the first gate electrode;
• a first inner gate spacer laterally surrounding the first dielectric gate liner;
• a contoured gate capping dielectric comprising a vertically-extending portion that laterally surrounds the first inner gate spacer and a first horizontally-extending portion that overlies the first gate electrode;
• and
• a first outer gate spacer laterally surrounding the contoured gate capping dielectric,
• and wherein the second field effect transistor comprises:
• a second source region and a second drain region embedded in a second portion of the semiconductor substrate;
• a second gate dielectric and a second gate electrode;
• a second dielectric gate liner laterally surrounding the second gate electrode and having a same material composition as the first dielectric gate liner;
• a second inner gate spacer laterally surrounding the second dielectric gate liner and having a same material composition as the first inner gate spacer;
• and
• a second outer gate spacer laterally surrounding the second inner gate spacer and having a same material composition as the first outer gate spacer, wherein the second outer gate spacer is in contact with the second inner gate spacer or is spaced from the second inner gate spacer by a native oxide layer having a thickness less than 1 nm;
• and
• a contact-level dielectric layer in contact with a surface segment of the contoured gate capping dielectric over the first gate electrode and in contact with surface segments of the first outer gate spacer outside an area of the first gate electrode.

A method of forming a semiconductor structure, the method comprising:

• forming a first gate dielectric and a first gate electrode over a first portion of a semiconductor substrate;
• forming a combination of a first dielectric gate liner and a first inner gate spacer around the first gate electrode;
• forming a combination of a contoured gate capping dielectric and a first outer gate spacer, wherein the contoured gate capping dielectric comprises a vertically-extending portion that laterally surrounds the first inner gate spacer and a first horizontally-extending portion that overlies the first gate electrode, and the first outer gate spacer laterally surrounds the contoured gate capping dielectric;
• forming a first source region and a first drain region in the first portion of the semiconductor substrate adjacent to the combination of the contoured gate capping dielectric and the first outer gate spacer;
• and
• forming a contact-level dielectric layer on a surface segment of the contoured gate capping dielectric over the first gate electrode and on the first outer gate spacer outside an area of the first gate electrode.