US 12,641,780 B2Granted

Three-dimensional flash memory device and method for forming the same

AssigneeWinbond Electronics Corp.

InventorFrederick Chen

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Abstract

A three-dimensional (3D) flash memory device is provided. The 3D flash memory device includes a substrate, a T-shaped polysilicon pillar, a select line pillar, a bit line pillar, first and second control gates, first and second floating gates, and first and second high-k dielectric pillars. The select line pillar and the bit line pillar are vertically disposed adjacent to first opposite sidewalls of the horizontally protruding portion on the substrate. The first control gate and the second control gate are positioned adjacent to second opposite sidewalls of the horizontally protruding portion. The first and second floating gates are laterally disposed between the horizontally protruding portion and the first and second control gates. The first and second high-k dielectric pillars are laterally disposed between the first floating gate and the first control gate, as well as between the second floating gate and the second control gate.

Claims16

Dependent claims

A three-dimensional flash memory device, comprising:

a substrate;
a T-shaped polysilicon pillar disposed on the substrate, wherein the T-shaped polysilicon pillar comprises a horizontally protruding portion extending substantially parallel to a top surface of the substrate and a vertically extending portion extending substantially vertical to the top surface of the substrate;
a select line pillar and a bit line pillar vertically disposed on the substrate, wherein the select line pillar and the bit line pillar are adjacent to first opposite sidewalls of the horizontally protruding portion;
a first control gate and a second control gate respectively adjacent to second opposite sidewalls of the horizontally protruding portion;
a first floating gate laterally disposed between the horizontally protruding portion and the first control gate;
a second floating gate laterally disposed between the horizontally protruding portion and the second control gate;
a first high-k dielectric pillar vertically disposed on the substrate and laterally disposed between the first floating gate and the first control gate;
and
a second high-k dielectric pillar vertically disposed on the substrate and laterally disposed between the second floating gate and the second control gate.

6 more elements

A three-dimensional flash memory device, comprising:

an alternating stack of insulating layers and polysilicon layers disposed over a substrate;
a polysilicon pillar extending through the alternating stack;
first insulating pillars extending through the alternating stack and adjacent to first opposite sidewalls of a horizontally protruding portion of the polysilicon pillar;
a select line pillar and a bit line pillar respectively extending through the first insulating pillars and adjacent to the first opposite sidewalls of the polysilicon pillar;
a first control gate and a second control gate respectively adjacent to second opposite sidewalls of the horizontally protruding portion of the polysilicon pillar and separated from the horizontally protruding portion of the polysilicon pillar by a first floating gate and a second floating gate;
a first high-k dielectric pillar extending through the alternating stack and interposed between the first control gate and the first floating gate;
and
a second high-k dielectric pillar extending through the alternating stack and interposed between the second control gate and the second floating gate.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/156,977Filed 19 Jan 2023
Published: US 2024/0251550 A125 Jul 2024
Granted: 26 May 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/10
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the top-view layout
H10B 41/20
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by three-dimensional [3D] arrangements, e.g.…
H10D 30/689
Floating-gate IGFETs: vertical floating-gate IGFETs