Serialization circuitry having an integrated buffer for a serializer/derserilizer communication system

A communication system comprising:

• transmitter circuitry configured to receive a data signal and output a serial data signal, the transmitter circuitry comprising:
• serializer circuitry comprising:
• data input circuitry configured to receive and output a first data signal based on a write pointer signal having a first value of values and a first clock signal;
• and
• data serializer circuitry configured to serialize the first data signal to generate a serial signal based on a read pointer signal having a second value of the values and a second clock signal, wherein generating the serial signal comprises outputting a first bit based on an inverted second clock signal and storing a second bit of the first data signal based on the second clock signal, and wherein the first value differs from the second value;
• and
• receiver circuitry configured to receive the serial data signal from the transmitter circuitry.