Delay line monitoring to maintain a data eye
AssigneeSilicon Laboratories Inc.
InventorsPaul Zavalney, Tak Ying Wong, Harikrishnan Prabha Valsala, Pio Balmelli
Life of this patent
Estimating the term…
Abstract
In one aspect, an apparatus includes: a delay line to receive a clock signal and a plurality of settings, each of the settings to indicate a selected tap of the delay line at which to output the clock signal. The delay line is to output a capture clock based on a first setting, and monitor clocks based on additional settings. The apparatus also includes: a data sampler to sample incoming data with the capture clock and output capture data; monitor samplers to sample the incoming data with the monitor clocks and output monitored data; and a monitor circuit to trigger an update to at least one of the settings based on comparison of the capture data to the monitored data.
Claims16
An apparatus comprising:
- a delay line comprising a plurality of taps, the delay line to receive a clock signal and a plurality of settings, each of the plurality of settings to indicate a selected tap at which to output the clock signal, wherein the delay line is to output a capture clock based on a first setting, a first monitor clock based on a second setting, and a second monitor clock based on a third setting;
- a data sampler to sample incoming data with the capture clock and output capture data;
- a first monitor sampler to sample the incoming data with the first monitor clock and output first monitored data;
- a second monitor sampler to sample the incoming data with the second monitor clock and output second monitored data;
- and
- a monitor circuit coupled to the first monitor sampler and the second monitor sampler, the monitor circuit to trigger an update to at least one of the plurality of settings based on comparison of the capture data to at least one of the first monitored data or the second monitored data, wherein the delay line further comprises a control circuit, the control circuit to adjust one or more of the plurality of settings in response to a signal from the monitor circuit.
A method comprising:
- receiving, in receiver circuitry of an integrated circuit, incoming data via a link;
- sampling the incoming data with:
- a capture clock to capture the incoming data as capture data;
- a first monitor clock to capture the incoming data as first monitored data;
- and
- a second monitor clock to capture the incoming data as second monitored data, wherein the capture clock, the first monitor clock and the second monitor clock are derived from a common clock signal provided to a delay line comprising a plurality of taps;
- and
- in response to a mismatch between the capture data and the first monitored data, triggering an interrupt and updating at least one configuration setting of the delay line to cause the capture clock to move away from the first monitor clock.
An integrated circuit comprising:
- at least one digital signal processor;
- and
- an interface circuit coupled to the at least one digital signal processor, the interface circuit to communicate with at least one device coupled to the integrated circuit via a link, the interface circuit comprising:
- a delay line to receive a clock signal and, based on a plurality of configuration settings, output a capture clock, a first monitor clock, and a second monitor clock;
- a plurality of receivers coupled to the delay line, each of the plurality of receivers to receive a bit of a multi-bit communication, each of the plurality of receivers comprising:
- a data sampler to sample the bit with the capture clock and output a capture bit;
- a first monitor sampler to sample the bit with the first monitor clock and output a first monitored bit;
- a second monitor sampler to sample the bit with the second monitor clock and output a second monitored bit;
- and
- monitor circuitry coupled to the first monitor sampler and the second monitor sampler, the monitor circuitry to compare the capture bit to at least one of the first monitored bit or the second monitored bit;
- and
- a controller coupled to the monitor circuitry, wherein in response to a mismatch between the capture bit and the at least one of the first monitored bit or the second monitored bit, the controller is to cause an update to at least one of the plurality of configuration settings, and the delay line, in response to the update to the at least one of the plurality of configuration settings of the delay line, is to cause the capture clock to move with respect to at least one of the first monitor clock or the second monitor clock.
Dependencies are inferred from the claim text.