System and method for error-detecting code-based packet transmission acknowledgement

A computing system comprising:

• a memory;
• and
• a processor configured to:
• process a plurality of packets transmitted from a first computing device to a second computing device;
• identify a packet sequence number associated with each packet;
• generate cyclic redundancy check (CRC) using the packet sequence number of each packet;
• compare the CRC with a CRC generated from a sequence of expected packet sequence numbers associated with transmission of a plurality of expected packets;
• and
• generate a notification indicating that a packet is missing from the plurality of expected packets.

A computer program product residing on a non-transitory computer readable medium having a plurality of instructions stored thereon which, when executed by a processor, cause the processor to perform operations comprising:

• processing a plurality of remote direct memory access (RDMA) packets transmitted from a first computing device to a second computing device;
• identifying a packet sequence number associated with each packet;
• generating an error-detecting code representation using the packet sequence number of each packet;
• comparing the error-detecting code representation with an error-detecting code representation generated from a sequence of expected packet sequence numbers associated with transmission of a plurality of expected packets;
• and
• generating a notification indicating that a packet is missing from the plurality of expected packets.