Systems and methods for data signal multiplexing

A method comprising:

• receiving a first sequence of 8 clock signals each having:
• a period of 8-unit intervals (UIs);
• an on-state spanning 2 UIs;
• and
• an off-state spanning 6 UIs, the 8 clock signals including:
• a first clock signal;
• a second signal delayed by 1 UI with respect to the first clock signal;
• a third clock signal delayed by 1 UI with respect to the second clock signal;
• a fourth clock signal delayed by 1 UI with respect to the third clock signal;
• a fifth clock signal delayed by 1 UI with respect to the fourth clock signal;
• a sixth clock signal delayed by 1 UI with respect to the fifth clock signal;
• a seventh clock signal delayed by 1 UI with respect to the sixth clock signal;
• and
• an eighth clock signal delayed by 1 UI with respect to the seventh clock signal;
• forming a first interleaved signal by providing, at an output of a first digital to analog converter (DAC):
• a first analog signal output in accordance with the first clock signal;
• a first reset signal output in accordance with the second clock signal;
• a second analog signal output in accordance with the third clock signal;
• a second reset signal output in accordance with the fourth clock signal;
• a third analog signal output in accordance with the fifth clock signal;
• a third reset signal output in accordance with the sixth clock signal;
• a fourth analog signal output in accordance with the seventh clock signal;
• and
• a fourth reset signal output in accordance with the eighth clock signal;
• generating a second sequence of 8 clock signals by:
• delaying the first clock signal by 1 UI to obtain a delayed first clock signal;
• delaying the second clock signal by 1 UI to obtain a delayed second clock signal;
• delaying the third clock signal by 1 UI to obtain a delayed third clock signal;
• delaying the fourth clock signal by 1 UI to obtain a delayed fourth clock signal;
• delaying the fifth clock signal by 1 UI to obtain a delayed fifth clock signal;
• delaying the sixth clock signal by 1 UI to obtain a delayed sixth clock signal;
• delaying the seventh clock signal by 1 UI to obtain a delayed seventh clock signal;
• and
• delaying the eighth clock signal by 1 UI to obtain a delayed eighth clock signal;
• forming a second interleaved signal by providing, at an output of a second digital to analog converter:
• a fifth analog signal output in accordance with the delayed first clock signal;
• a fifth reset signal output in accordance with the delayed second clock signal;
• a sixth analog signal output in accordance with the delayed third clock signal;
• a sixth reset signal output in accordance with the delayed fourth clock signal;
• a seventh analog signal output in accordance with the delayed fifth clock signal;
• a seventh reset signal output in accordance with the delayed sixth clock signal;
• an eighth analog signal output in accordance with the delayed seventh clock signal;
• and
• an eighth reset signal output in accordance with the delayed eighth clock signal;
• and
• combining the first interleaved signal with the second interleaved signal.

An apparatus for data signal multiplexing, comprising:

• a first 4:1 multiplexer (MUX) configured to:
• receive a first set of four analog signals from a first group of four digital-to-analog converters (DACs);
• and
• interleave the first set of four analog signals to generate a first interleaved analog output, wherein the first interleaved analog output is based on a first 8-unit interval (8 UI) window comprising four consecutive 2 UI windows, each 2 UI window corresponding to an analog signal of the first set of four analog signals and including a one-unit interval (1 UI) of data output followed by a 1 UI of reset to a common mode level;
• a second 4:1 MUX configured to:
• receive a second set of four analog signals from a second group of four DACs;
• and
• interleave the second set of four analog signals to generate a second interleaved analog output, wherein the second interleaved analog output is based on a second 8 UI window comprising four consecutive 2 UI windows, each 2 UI window corresponding to an analog signal of the second set of four analog signals and including a 1 UI of data output followed by a 1 UI of reset to a common mode level, and wherein the second interleaved analog output is offset by one UI relative to the first interleaved analog output;
• and
• a 2:1 MUX configured to:
• receive the first interleaved analog output from the first 4:1 MUX and the second interleaved analog output from the second 4:1 MUX;
• and
• interleave the first interleaved analog output and the second interleaved analog output to generate a combined interleaved analog output, wherein each interleaving in the 2:1 MUX comprises a 1 UI of data output from the first interleaved output followed by a 1 UI of data output from the second interleaved output.