System and method for phase alignment between multiple phase-locked loops circuits

A method, comprising:

• in a system including a plurality of phase-locked loop (PLL) circuits,
• wherein each of the plurality of PLL circuits includes a reference buffer, a phase detector and charge pump, a phase shifter, and a delta sigma (ΔΣ) modulator, and
• wherein each of the plurality of PLL circuits is configured to receive a reference frequency signal and output a plurality of output signals:
• determining phase difference information between a first output signal of the plurality of output signals of one of the plurality of PLL circuits and a second output signal of the plurality of output signals of other of the plurality of PLL circuits,
• determining control information based on the determined phase difference information between the first output signal and the second output signal,
• controlling at least one of the reference buffer, the phase detector and charge pump, the phase shifter, or the delta sigma (ΔΣ) modulator of the one of the plurality of PLL circuits based on the determined control information, and
• controlling phase alignment between the first output signal of the one of the plurality of PLL circuits and the second output signal of the other of the plurality of PLL circuits based on the control of the at least one of the reference buffer, the phase detector and charge pump, the phase shifter, or the delta sigma (ΔΣ) modulator.

An electronic device, comprising:

• at least one processor coupled to a plurality of phase-locked loop (PLL) circuits,
• wherein each of the plurality of PLL circuits includes a reference buffer, a phase detector and charge pump, a phase shifter, and a delta sigma (ΔΣ) modulator,
• wherein each of the plurality of PLL circuits is configured to receive a reference frequency signal and output a plurality of output signals;
• and
• wherein the at least one processor is configured to:
• determine phase difference information between a first output signal of the plurality of output signals of one of the plurality of PLL circuits and a second output signal of the plurality of output signals of other of the plurality of PLL circuits,
• determine control information based on the determined phase difference information between the first output signal and the second output signal,
• control at least one of the reference buffer, the phase detector and charge pump, the phase shifter, or the delta sigma (ΔΣ) modulator of the one of the plurality of PLL circuits based on the determined control information, and
• control phase alignment between the first output signal of the one of the plurality of PLL circuits and the second output signal of the other of the plurality of PLL circuits based on the control of the at least one of the reference buffer, the phase detector and charge pump, the phase shifter, or the delta sigma (ΔΣ) modulator.