A high-frequency crystal oscillator based on an automatic phase error correction, wherein the high-frequency crystal oscillator includes a high-frequency crystal, a first load capacitor, a second load capacitor, a ring oscillator, an eight-frequency-dividing circuit, a twisted ring counter, a peak detector, a buffer, a digital module, a multiplexer, an amplifier, a first single-pole double-throw switch and a second single-pole double-throw switch;
- one terminal of the high-frequency crystal is recorded as an XOIN, and another terminal of the high-frequency crystal is recorded as an XOOUT;
- a fixed terminal of the first single-pole double-throw switch is in connection with the terminal XOIN of the high-frequency crystal, a first moving terminal of the first single-pole double-throw switch is in connection with the multiplexer, and a second moving terminal of the first single-pole double-throw switch is in connection with one terminal of the first load capacitor and an input terminal of the amplifier;
- a fixed terminal of the second single-pole double-throw switch is in connection with the terminal XOOUT of the high-frequency crystal, a first moving terminal of the second single-pole double-throw switch is in connection with the peak detector, a second moving terminal of the second single-pole double-throw switch is in connection with one terminal of the second load capacitor and an output terminal of the amplifier, and another terminals of the first and second load capacitors are both grounded;
- when the high-frequency crystal oscillator is started, a digital module is adopted to generate a switch control signal ENINJ for controlling the fixed terminal of the first single-pole double-throw switch to be in connection with the first moving terminal of the first single-pole double-throw switch, and controlling the fixed terminal of the second single-pole double-throw switch to be in connection with the first moving terminal of the second single-pole double-throw switch;
- and the ring oscillator is configured to generate a square wave signal F64×, and transmit the square wave signal to the eight-frequency-dividing circuit and the peak detector;
- the eight-frequency-dividing circuit is configured to divide the square wave signal to generate a frequency-dividing signal F8×, and transmit the F8× to the twisted ring counter, and the twisted ring counter is configured to divide the F8× again to generate eight signals Phase[7:0] with a same frequency and different phases, and transmit the signals Phase[7:0] to the multiplexer;
- the peak detector is further configured to receive a signal PKDIN output by the terminal XOOUT of the high-frequency crystal, and the peak detector is configured to take the square wave signal F64× as a high-frequency operating clock, reflect a peak position of the signal PKDIN by outputting a pulse signal PKDOUT, and transmit the pulse signal PKDOUT to the buffer;
- and the buffer is configured to expand a negative pulse width of the pulse signal PKDOUT and transmit a BUFFOUT to the digital module after an expanded pulse signal BUFFOUT is obtained;
- the digital module is configured to generate initial control signals EN[7:0], the control signals EN[7:0] are eight-bit control signals, the digital module is configured to switch the control signals EN[7:0] by discriminating an edge relation between a signal PDIN and the signal BUFFOUT, and transmit the switched control signals EN[7:0] to the multiplexer;
- the multiplexer is configured to select one signal from signals Phase[7:0] according to a magnitude of the frequency of the square wave signal F64× and the control signals EN[7:0] and record as the signal PDIN to input into the digital module;
- the multiplexer is further configure to select one signal from the signals Phase[7:0] as an injection signal according to the control signals EN[7:0] to inject into the terminal XOIN of the high-frequency crystal through the first single-pole double-throw switch, and the injection signal is coupled to the terminal XOOUT through the high-frequency crystal, and is superimposed with a high-frequency oscillation signal FOSC generated by the high-frequency crystal at the terminal XOOUT to obtain the signal PKDIN, and the signal PKDIN is input to the peak detector through the second single-pole double-throw switch;
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- in a maintenance stage, the switch control signal ENINJ is for controlling the fixed terminal of the first single-pole double-throw switch to be in connection with the second moving terminal of the first single-pole double-throw switch, and controlling the fixed terminal of the second single-pole double-throw switch to be in connection with the second moving terminal of the second single-pole double-throw switch.