Optimization method and apparatus for program/erase voltage of charge-trap memory devices through 3D trap analysis

A computing device for optimizing a program voltage and an erase voltage of a charge-trap memory device through a three-dimensional (3D) trap analysis, the computing device comprising:

• a memory;
• and
• a processor configured to connect to the memory, and to execute at least one instruction stored in the memory,
• wherein the processor is configured to,
• by a measurement module, apply each of different trap control voltages to the memory device and measure low-frequency noises of the memory device respectively corresponding to the trap control voltages,
• extract a trap distribution in the memory device for each of the trap control voltages based on the low-frequency noises, respectively, and
• analyze the trap distributions according to depths of the memory device, and determine a target trap control voltage having a maximum trap distribution in a charge trap layer of the memory device,
• wherein the low-frequency noises include noise that occurs in a drain current of the memory device and noise corresponding to a flat band voltage of the memory device, respectively corresponding to the trap control voltages,
• wherein the processor is configured to extract the trap distribution by
• extracting the trap distribution in the memory device for each of the trap control voltages using a spectrum density of the noise that occurs in the drain current and a spectrum density of the noise corresponding to the flat band voltage, and
• wherein the processor is configured to determine the target trap control voltage by
• verifying the trap distribution according to a depth belonging to the charge trap layer for each of the trap control voltages, based on a relationship between the trap distribution and the depths belonging to the charge trap layer, and
• determining a trap control voltage exhibiting the maximum trap distribution from among the trap control voltages as the target trap control voltage, based on a result of comparing the trap distribution according to the depth belonging to the charge trap layer among the trap control voltages.