Host-to-device interface circuitry testing

A method for testing an integrated circuit, the method comprising:

• storing test data in memory of the integrated circuit over interface circuitry configured to communicate test data between a device outside of the integrated circuit and the integrated circuit;
• and
• entering a self-test mode, wherein the self-test mode:
• isolates circuitry other than the interface circuitry from testing and prevents communication with the device outside of the integrated circuit, and
• tests the interface circuitry using the test data retrieved from the memory of the integrated circuit by applying the test data as input to the interface circuitry and comparing output produced by the interface circuitry with expected output data stored in the memory.

An integrated circuit configured for storing data, comprising:

• interface circuitry configured to communicate data between a device outside of the integrated circuit and the integrated circuit and storage circuitry configured to store a first portion of the data in a first memory via built-in self-test (BIST) circuitry of the first memory while incrementing a first BIST counter of the first memory until the first BIST counter reaches a terminal saturation count and asserts a hardware trigger;
• circuitry configured to, responsive to the asserted hardware trigger, store a second portion of the data in a second memory via BIST circuitry of the second memory while incrementing a second BIST counter of the second memory until the second BIST counter reaches a terminal saturation count;
• and
• test circuitry configured to place the integrated circuit in a self-test mode, wherein the self-test mode:
• isolates circuitry other than the interface circuitry from testing, and
• tests the interface circuitry based on the first portion and the second portion.