Bit counting circuits and memory devices including the same

A nonvolatile memory device comprising:

• a memory cell array including a plurality of memory cells;
• a plurality of page buffers connected to the memory cell array through bit lines;
• a control logic configured to generate a clock signal;
• a page buffer selection signal control circuit configured to generate a page buffer selection signal including information about a ratio of a number of page buffers on which a fail bit counting operation is performed to a total number of the plurality of page buffers;
• a fail bit counting circuit configured to:
• select, based on the clock signal and the page buffer selection signal, one or more page buffers from among the plurality of page buffers, repeat, based on a shift register, the fail bit counting operation on the selected one or more page buffers, and output a value of a number of fail bits with respect to the selected one or more page buffers on which the fail bit counting operation is performed based on the repetition;
• and
• a predictor configured to generate, based on the ratio of the number of page buffers on which the fail bit counting operation is performed to the total number of the plurality of page buffers and the number of fail bits with respect to the selected one or more page buffers on which the fail bit counting operation is performed, a prediction value with respect to a total number of fail bits with respect to the plurality of page buffers.

An operating method of a nonvolatile memory device including a plurality of page buffers, the operating method comprising:

• selecting one or more page buffers from among the plurality of page buffers and repeating a fail bit counting operation on the selected one or more page buffers based on a shift register;
• generating a value of a number of fail bits with respect to the selected one or more page buffers on which the fail bit counting operation is performed based on the repetition;
• and
• generating, based on a ratio of a number of the selected one or more page buffers on which the fail bit counting operation is performed to a total number of the plurality of page buffers and the number of fail bits with respect to the selected one or more page buffers on which the fail bit counting operation is performed, a prediction value with respect to a total number of fail bits with respect to the plurality of page buffers.