Memory device storing a first, second, and third bit

A memory device comprising:

• a memory cell coupled to a bit line and a word line and configured to store first data including a first bit, a second bit, and a third bit;
• and
• a sense amplification circuit configured to perform a first comparison between a bit line voltage of the bit line and a first reference voltage, and a second comparison between the bit line voltage and a second reference voltage lower than the first reference voltage, and to read the first data from the memory cell based on a result of the first comparison and a result of the second comparison,
• wherein the sense amplification circuit is configured to
• retain second data having a first code in response to the bit line voltage becoming equal to or lower than the first reference voltage during a first period from a start of operation of the sense amplification circuit to a first time point, and
• retain the first data after the first period.