Amplitude modulation for writing to a multi-level bit-cell

An apparatus comprising:

• a first circuitry to voltage boost a word-line above a nominal voltage to generate a boosted word-line, wherein the boosted word-line has a first pulse width, wherein the word-line is coupled to a gate terminal of a transistor, wherein the transistor is further coupled to a bit-line, wherein the transistor is coupled to a capacitor, and wherein the capacitor has a first terminal coupled to a plate-line and a second terminal coupled to the transistor;
• and
• a second circuitry to write a first state and a second state to the capacitor in a first write phase via amplitude modulation of the bit-line and by assertion of the plate-line between a duration of a first pulse of the word-line to generate an asserted plate-line, wherein the asserted plate-line has a second pulse shorter than the first pulse.