Memory array with multiplexed digit lines
AssigneeMicron Technology, Inc.
InventorsFerdinando Bedeschi, Stefan Frederik Schippers
Life of this patent
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Abstract
Methods, systems, and devices for a memory device with multiplexed digit lines are described. In some cases, a memory cell of the memory device may include a storage component and a selection component that includes two transistors. A first transistor may be coupled with a word line and a second transistor may be coupled with a select line to selectively couple the memory cell with a digit line. The selection component, in conjunction with a digit line multiplexing component, may support a sense component common to a set of digit lines. In some cases, the digit line of the set may be coupled with the sense component during a read operation, while the remaining digit lines of the set are isolated from the sense component.
Claims18
A memory device, comprising:
- a memory cell coupled with a digit line and a plate line, the memory cell comprising a storage component, a first transistor coupled with the storage component and the digit line, and a second transistor coupled with the storage component and the plate line;
- a word line coupled with a gate of the first transistor and configured to selectively couple the storage component with the digit line;
- a select line coupled with a gate of the second transistor and configured to selectively couple the storage component with the plate line;
- a sense component configured to selectively couple with a plurality of digit lines comprising the digit line;
- and
- a third transistor coupled with the select line and configured to selectively couple the digit line with the sense component during at least a portion of a read operation.
A memory device, comprising:
- a memory cell coupled with a digit line and a plate line, the memory cell comprising a storage component and two transistors connected in a series configuration;
- a word line coupled with a gate of a first transistor of the two transistors and configured to select the memory cell;
- a select line coupled with a gate of a second transistor of the two transistors and configured to couple the memory cell with the digit line;
- a sense component configured to selectively couple with a plurality of digit lines comprising the digit line;
- and
- a third transistor coupled with the select line and configured to selectively couple the digit line with the sense component during at least a portion of a read operation.
A memory device, comprising:
- a memory cell comprising a storage component, a first transistor, and a second transistor, wherein the first transistor and the second transistor are coupled with the storage component;
- a word line coupled with the memory cell;
- a digit line coupled with the first transistor of the memory cell and extending in a first direction;
- a select line coupled with the second transistor of the memory cell, the select line configured to selectively couple the memory cell with the digit line;
- a sense component configured to be selectively coupled with a plurality of digit lines that comprise the digit line;
- and
- a third transistor configured to selectively couple the digit line with the sense component, a gate of the third transistor coupled with the select line.
Dependencies are inferred from the claim text.