Strobe delay calibration for unmatched receive memory
AssigneeIntel Corporation
InventorsChia How Low, Roger Cheng, Aaron K. Martin
Life of this patent
Estimating the term…
Abstract
An apparatus, system, and method for improved memory control are provided. A circuit can include controller circuitry configured to determine, based on a speed of silicon of a memory, a read strobe code that adjusts a data clock to account for a difference between a reference clock and a data clock in terms of a number of unit intervals (UIs) and a read strobe code, a receive delay locked loop to receive the difference and delay the data clock by the number of UI and read strobe codes resulting in a delayed data clock, and a sampling amplifier to sample data from the memory based on the delayed data clock.
Claims20
A memory control circuit comprising:
- controller circuitry configured to determine, based on a speed of silicon of a memory, a read strobe code and a number of unit intervals (UIs), a combination of which indicates an adjustment to a data clock to account for a difference between a reference clock and a data clock in terms of the number of UIs and the read strobe code, a single UI of the UIs is a maximum extent of a fine delay adjustment provided by a receive delay locked loop and the number of UIs constitutes a coarse adjustment to the data clock, the read strobe code is the fine delay adjustment to the data clock having multiple steps and delays the data clock by less than the single UI;
- a receive delay locked loop to receive the difference and delay the data clock by the number of UIs and read strobe code resulting in a delayed data clock that is calibrated to line up an edge of the delayed data clock with an edge of the reference clock;
- and
- a sampling amplifier to sample data from the memory based on the delayed data clock.
A device comprising:
- a memory;
- controller circuitry configured to determine, based on a speed of silicon of the memory, a read strobe code and a number of unit intervals (UIs), a combination of which indicates an adjustment to a data clock to account for a difference between a reference clock and a data clock in terms of the number of UIs and the read strobe code, a single UI of the UIs is a maximum extent of a fine delay adjustment provided by a receive delay locked loop and the number of UIs constitutes a coarse adjustment to the data clock, the read strobe code is the fine delay adjustment to the data clock having multiple steps and delays the data clock by less than the single UI;
- a receive delay locked loop situated to receive the difference and delay the data clock by the number of UIs and the read strobe code resulting in a delayed data clock that is calibrated to line up an edge of the delayed data clock with an edge of the reference clock;
- and
- a sampling amplifier to sample data from the memory based on the delayed data clock.
A method for memory control, the method comprising:
- determining, by controller circuitry, based on a speed of silicon of a memory, a read strobe code and a number of unit intervals (UIs), a combination of which indicates an adjustment to a data clock to account for a difference between a reference clock and a data clock in terms of the number of UIs and the read strobe code, a single UI of the UIs is a maximum extent of a fine delay adjustment provided by a receive delay locked loop and the number of UIs constitutes a coarse adjustment to the data clock, the read strobe code is the fine delay adjustment to the data clock having multiple steps and delays the data clock by less than the single UI;
- receiving, by a receive delay locked loop, the difference;
- delaying, by the receive delay locked loop, the data clock by the number of UIs and the read strobe code resulting in a delayed data clock that is calibrated to line up an edge of the delayed data clock with an edge of the reference clock;
- and
- sampling, by a sampling amplifier, to data from the memory based on the delayed data clock.
Dependencies are inferred from the claim text.