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US 12,640,181 B2Granted
Low error rate read operation in multi-module arrays
AssigneeSanDisk Technologies LLC
InventorsKadriye Deniz Bozdag, Juan Saenz, Mark Lin, Dimitri Houssameddine, Mario Laudato, Nicolas Irizarry, Ashraf B. Islam
Life of this patent
Estimating the term…
Abstract
Technology for reading memory cells in a cross-point architecture. A memory system reads one memory cell in each module in parallel. The memory system performs two reads of the memory cells with a first read using a first reference signal and a second read using a second reference signal instead of the first reference signal. The second reference signal has a different magnitude from the first reference signal in order to compensate for differences between the modules.
Claims15
An apparatus, comprising:
- a control circuit configured to communicate with cross-point memory arrays, each cross-point memory array having programmable resistance memory cells, the control circuit configured to:
- perform a first read of a group of the memory cells that store one or more error correcting code (ECC) codewords, wherein each memory cell in the group is in a different cross-point memory array, the first read performed using a first reference signal to generate first read results for the group, the group includes a first subset of the group and a second subset of the group;
- apply an error correction algorithm to the first read results;
- provide decoded data to a host responsive to successfully decoding the first read results with the error correction algorithm;
- perform a second read of at least the second subset of the group of memory cells using a second reference signal instead of the first reference signal to generate second read results, the second reference signal having a different magnitude than the first reference signal;
- replace the first read results for the memory cells in the second subset with the second read results for the memory cells in the second subset to form final read results for the group that includes the first read results for memory cells in the first subset and the second read results for memory cells in the second subset;
- apply the error correction algorithm to the final read results if decoding the first read results failed;
- and
- provide decoded data to the host responsive to successfully decoding the final read results with the error correction algorithm.
6 more elements
A method for reading memory cells, the method comprising:
- sensing a group of programmable resistance memory cells on a memory die to generate first sensing results, the memory die having a plurality of modules of programmable resistance memory cells, the memory cells in each respective module sharing a common set of addresses within the respective module, each cell in the group having the same address in a different module, the group of programmable resistance memory cells store one or more error correcting code (ECC) codewords;
- comparing the first sensing results with a first reference signal to generate first read results;
- providing the first read results to an ECC engine;
- determining that decoding the first read results failed responsive to the ECC engine failing to successfully decode the first read results;
- sensing at least a subset of the group to generate second sensing results;
- comparing the second sensing results with a second reference signal to generate second read results, the second reference signal having a different magnitude than the first reference signal;
- replacing the first read results for memory cells in the subset with the second read results for the memory cells in the subset to generate final read results;
- providing the final read results to the ECC engine;
- and
- providing successfully decoded data for the one or more ECC codewords to a host responsive to the ECC engine successfully decoding the final read results.
7 more elements
A memory system, comprising:
- a plurality of cross-point memory arrays, each cross-point memory array having programmable resistance memory cells;
- a first set of capacitors and a second set of capacitors, there being a capacitor in the first set and a capacitor in the second set for each cross-point memory array;
- and
- one or more control circuits in communication with the plurality of cross-point memory arrays, the first set of capacitors and the second set of capacitors, the one or more control circuits configured to:
- sense a group of the memory cells that store one or more error correcting code (ECC) codewords to generate sense signals, wherein each memory cell in the group is in a different cross-point memory array of the plurality of cross-point memory arrays, the group of the memory cells includes a first subset and a second subset;
- store the sense signals on the first set of capacitors and the second set of capacitors;
- compare the sense signals from the first set of capacitors to a first reference signal to generate first read results;
- compare the sense signals from the second set of capacitors to a second reference signal to generate second read results, the second reference signal having a different magnitude than the first reference signal;
- and
- form final read results for the group that includes the first read results for memory cells in the first subset and the second read results for memory cells in the second subset.
7 more elements
Dependencies are inferred from the claim text.