Memory circuit, interface circuit for memory circuit, and method of operating memory circuit

An interface circuit for a memory circuit, the interface circuit comprising:

• a first counter circuit comprising:
• an input coupled to a control signal input,
• a clock input coupled to a clock signal input, and
• an output;
• a first latch circuit comprising:
• an input coupled to the output of the first counter circuit,
• a clock input coupled to the clock signal input, and
• an output;
• a second counter circuit comprising:
• a clock input coupled to the clock signal input, and
• an output;
• a first comparator circuit comprising:
• a first input coupled to the output of the first latch circuit,
• a second input coupled to the output of the second counter circuit, and
• an output;
• and
• a second latch circuit comprising:
• a clock input coupled to the output of the first comparator circuit, and an output.

A method of operating a memory circuit, the method comprising:

• in response to a single pulse of a control signal, generating
• a series of internal clock pulses,
• a first access signal different from the series of internal clock pulses, and
• a second access signal different from the first access signal and the series of internal clock pulses;
• and
• performing at least one of a read operation or a program operation in the memory circuit, based on
• the first access signal,
• the second access signal, and
• at least one internal clock pulse in the series of internal clock pulses.