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US 12,640,177 B2Granted
Storage device and data training method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsTongsung Kim, Seonkyoo Lee, Seungjun Bae, Taesung Lee
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Abstract
A storage device includes a first chip and a second chip configured to exchange data with the first chip. The first chip may transmit a data strobe signal and a plurality of data signals, applied with different delay times, to the second chip. The second chip may sample the plurality of data signals, applied with the different delay times, using the data strobe signal received from the first chip during data training.
Claims19
A storage device comprising:
- a first chip;
- and
- a second chip configured to exchange data with the first chip,
- wherein the first chip is configured to transmit a data strobe signal and a plurality of data signals to the second chip such that different delay times are applied to each of the plurality of data signals, and
- the second chip is configured to, during data training, sample the plurality of data signals using the data strobe signal received from the first chip,
- the data training including a coarse mode and a fine mode,
- the second chip is configured to generate a coarse initial code based on a sampling result in the coarse mode,
- the first chip is configured to determine a coarse data strobe signal (DQS) delay time based on the coarse initial code and to apply the coarse DQS delay time to the data strobe signal in the fine mode, and
- the first chip is configured to additionally apply the coarse DQS delay time to the plurality of data signals in the fine mode.
6 more elements
A storage device comprising:
- a controller;
- and
- a memory device configured to exchange data with the controller and comprising an interface circuit and a plurality of nonvolatile memories,
- wherein the controller is configured to transmit a plurality of first data signals and a first data strobe signal to the interface circuit during first data training, each of the plurality of first data signals applied with a different delay time,
- the interface circuit is configured to transmit a plurality of second data signals and a second data strobe signal to the plurality of nonvolatile memories during second data training, each of the plurality of second data signals applied with a different delay time, and
- a frequency of the second data strobe signal is lower than a frequency of the first data strobe signal.
3 more elements
Dependencies are inferred from the claim text.