System and method for improving efficiency of multi-storage-row compute-in-memory

A memory circuit, comprising:

• an array comprising a plurality of processing elements (PEs) arranged over a plurality of columns and a plurality of rows, wherein each of the PEs is configured to perform a multiplication and accumulation (MAC) operation on a corresponding one of a plurality of first data elements and a corresponding one of a plurality of second data elements;
• a fetch circuit coupled to the array and configured to fetch a first subset of the first data elements from a corresponding buffer, during a first cycle for the first subset of the first data elements to be written to a first subset of the PEs arranged along a first one of the rows;
• and
• a controller coupled to the fetch circuit and configured to cause the fetch circuit to limit fetching a second subset of the first data elements from the buffer, during a second subsequent cycle for the second subset of the first data elements to be written to a second subset of the PEs arranged along a second one of the rows.

A method for operating a compute-in-memory (CIM) circuit, comprising:

• receiving, through a buffer, a plurality of first data elements;
• fetching, through the buffer, a first subset of the first data elements and temporarily store the first subset of the first data elements, during a first cycle to write the first subset of the first data elements to a first subset of a plurality of processing elements (PEs);
• determining, through the buffer, whether to reuse at least one of the first subset of the first data elements based on a configuration of an artificial intelligence (AI) neural network associated with the plurality of first data elements;
• and
• selectively limit fetching, through the buffer, a second subset of the first data elements, during a second subsequent cycle to write the second subset of the first data elements to a second subset of the PEs, based on determination of whether to reuse the at least one of the first subset.