Thwarting control plane attacks with displaced and dilated address spaces

A computer processor, comprising:

• a memory, and
• a dedicated functional unit in a stage of a pipeline of the computer processor, the computer processor including an indirect jump (jalr) instruction that when executed by the dedicated functional unit causes the computer processor to:
• translate one or more pointers between displaced and dilated address space in a superimposed address space of the memory and virtual address space of the memory, wherein the displaced and dilated address space has been dilated by at least:
• dividing the virtual address space into segments of size Svas, where Svas denotes a segment size in bytes,
• inserting dummy memory holes of size i bytes, where i denotes an integer number of bytes, into each of the segments of size Svas;
• and
• mapping each of the segments of size Svas to a respective segment of the superimposed address space having size Sddas.

A computer processor, comprising:

• a memory, and
• a dedicated functional unit in a stage of a pipeline of the computer processor, the computer processor including a memory access instruction that when executed by the dedicated functional unit causes the computer processor to:
• translate one or more pointers between displaced and dilated address space in a superimposed address space of the memory and virtual address space of the memory, wherein the displaced and dilated address space has been dilated by at least:
• dividing the virtual address space into segments of size Svas, where Svas denotes a segment size in bytes,
• inserting dummy memory holes of size i bytes into each of the segments of size Svas, where i denotes an integer number of bytes;
• and
• mapping each of the segments of size Svas to a respective segment of the superimposed address space having size Sddas.