Integrated circuit

An integrated circuit comprising:

• two processing cores, wherein each processing core of the two processing cores comprises:
• a core controller operable to execute instructions to perform one or more processing tasks;
• a memory resource connected to the core controller;
• and
• a hardware accelerator module connected to the core controller, wherein the hardware accelerator module only obtains data from the memory resource via the core controller, wherein the core controller is configured to send an instruction signal to the hardware accelerator module via an interface, wherein the core controller is configured to send a verification signal to the hardware accelerator module to verify that the instruction signal is a valid signal;
• a shared bus connected to a respective hardware accelerator module of the two processing cores, wherein each hardware accelerator module of the two processing cores is configured to perform one or more cryptographic operations to encrypt the data provided by a respective core controller before forwarding the encrypted data to the shared bus;
• and
• a shared memory resource connected to the shared bus,
• wherein the only communication path between the two processing cores is via the hardware accelerator modules and the shared bus.