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US 12,639,231 B2Granted
Multi-level cache data tracking and isolation
AssigneeIntel Corporation
InventorsAneesh Aggarwal, Georgii Tkachuk, Subhiksha Ravisundar, Youngsoo Choi, Niall McDonnell
Life of this patent
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Abstract
An example of an apparatus may include a first cache organized as two or more portions, a second cache, and circuitry coupled to the first cache and the second cache to determine a designated portion allocation for data transferred from the first cache to the second cache, and track the designated portion allocation for the data transferred from the first cache to the second cache. Other examples are disclosed and claimed.
Claims17
An apparatus, comprising:
- a first cache comprising first ways and second ways;
- a second cache;
- and
- circuitry coupled to the first cache and the second cache, the circuitry to:
- identify a first allocation of the first ways to a first data type of multiple data types, wherein the first data type comprises an input/output (IO) data type;
- identify a second allocation of the second ways to a second data type of the multiple data types;
- detect that a first line is to be fetched from the first cache to a location at the second cache;
- where the first line is to be fetched from the first ways, provide a first value, with a bit at the location, to identify the first data type based on the first allocation;
- where the first line is to be fetched from the second ways, provide a second value, with the bit at the location, to identify the second data type based on the second allocation;
- perform a detection that the first line is to be evicted from the second cache to the first cache;
- perform a selection, based on the detection, between the first ways or the second ways based on the bit;
- and
- signal that the first line is to be evicted to a way of the first cache based on the selection.
10 more elements
At least one non-transitory machine readable medium comprising a plurality of instructions that, in response to being executed on a computing device, cause the computing device to:
- identify a first allocation of first ways to a first data type of multiple data types, wherein the first data type comprises an input/output (IO) data type;
- identify a second allocation of second ways to a second data type of the multiple data types, wherein a first cache comprises the first ways and the second ways;
- detect that a first line is to be fetched from the first cache to a location at a second cache;
- where the first line is to be fetched from the first ways, provide a first value, with a bit at the location, to identify the first data type based on the first allocation;
- where the first line is to be fetched from the second ways, provide a second value, with the bit at the location, to identify the second data type based on the second allocation;
- performing a detection that the first line is to be evicted from the second cache to the first cache;
- performing a selection, based on the detection, between the first ways or the second ways based on the bit;
- and
- signaling that the first line is to be evicted to a way of the first cache based on the selection.
6 more elements
An apparatus, comprising:
- a core that includes a core-level cache;
- a next-level cache comprising first ways and second ways;
- and
- circuitry coupled to the core-level cache and the next-level cache, the circuitry to:
- identify a first allocation of the first ways to a first data type of multiple data types, wherein the first data type comprises an input/output (IO) data type;
- identify a second allocation of the second ways to a second data type of the multiple data types;
- detect that a first line is to be fetched from the next-level cache to a location at the core-level cache;
- where the first line is to be fetched from the first ways, provide a first value, with a bit at the location, to identify the first data type based on the first allocation;
- where the first line is to be fetched from the second ways, provide a second value, with the bit at the location, to identify the second data type based on the second allocation;
- perform a detection that the first line is to be evicted from the core-level cache to the next-level cache;
- perform a selection, based on the detection, between the first ways or the second ways based on the bit;
- and
- signal that the first line is to be evicted to a way of the next-level cache based on the selection.
10 more elements
Dependencies are inferred from the claim text.