Transaction method and transaction system capable of reducing dynamic random-access memory traffic

A transaction system comprising:

• a first processing element;
• a second processing element;
• a cache coupled to the first processing element and the second processing element;
• and
• a microcontroller unit (MCU) coupled to the first processing element, the second processing element, and the cache;
• wherein the MCU assigns first buffer identifier (BID) information to the first processing element and the second processing element, the MCU initializes a first read counter of the MCU according to a first predefined read count, the first processing element writes data to the cache, the first processing element attaches a first sideband signal with the first BID information, the second processing element reads the data from the cache, the first BID information is appended with a first read done message, the second processing element transmits the first read done message to the MCU after the data of the cache is read by the second processing element, the MCU decrements the first read counter according to the first read done message, and the MCU transmits a first frame-discard cache maintenance operations (CMO) command to the cache in response to decrementing the first read counter to zero.