Failure recovery in a distributed coarse grained reconfigurable architecture
AssigneeSambaNova Systems, Inc.
InventorsPaul Jordan, Manish K. Shah
Life of this patent
Estimating the term…
Loading patent…
AssigneeSambaNova Systems, Inc.
InventorsPaul Jordan, Manish K. Shah
Estimating the term…
A computing system is disclosed, comprising a host computer and multiple CGRPs (coarse-grained reconfigurable architecture processors) connected to the host computer through external communication links. Each CGRP includes an internal network, external interface circuits, memory interface circuits, arrays of configurable units, hang detection circuits, force-quit controllers, and a network recovery circuit with control registers. The host computer is programmed to configure and execute applications across the arrays of configurable units in both CGRPs. In case of a hang detection in one CGRP, the network recovery circuit initiates a force quit process and notifies the host computer. Additionally, the network recovery circuit compares application IDs and halts execution in the other CGRP if necessary. This system provides efficient failure tolerance and recovery mechanisms for parallel processing applications.
A computing system comprising:
A reconfigurable processor, comprising:
A method of halting execution of an application within a reconfigurable processor having a first array of configurable units and a second array of configurable units, each coupled to an internal network of the reconfigurable processor and respectively comprising a plurality of processor configurable units and a plurality of memory configurable units coupled together with an array-level network, the reconfigurable processor including one or more CSRs (control/status registers) that include a first application ID field and a second application ID field, the method comprising:
Dependencies are inferred from the claim text.