Processor architecture for optimized parallelized search

A system, comprising:

• one or more processors to execute operations including:
• retrieving, from memory, a plurality of solutions pre-stored in memory for an optimized parallelized search computation corresponding to concurrent modification of the plurality of solutions, each solution of the plurality of solutions corresponding to a unique initial candidate of a plurality of unique initial candidates and representing a plurality of values in a multi-dimensional space;
• allocating, to one or more circuits of the one or more processors a first corresponding solution from the plurality of solutions, the first corresponding solution allocated for modification by a first corresponding circuit of the one or more circuits;
• allocating, to the one or more circuits of the one or more processors, a second corresponding solution of a second unique initial candidate from the plurality of solutions, the second corresponding solution allocated for modification by a second corresponding circuit of the one or more circuits;
• modifying, by the one or more circuits, at least one value of the first corresponding solution or the second corresponding solution of the plurality of solutions allocated to the one or more circuits to determine a plurality of modified solutions different from the plurality of solutions corresponding to the plurality of unique initial candidates retrieved from the memory;
• outputting, by the one or more circuits, a selected solution from the plurality of modified solutions, wherein selecting the selected solution comprises:
• determining a deviation metric of the plurality of modified solutions;
• and
• selecting, as the selected solution, a modified solution of the plurality of modified solutions based on the determined deviation metric;
• and
• causing a computation of one or more delivery navigation operations using the selected solution.

A method, comprising:

• retrieving, by a processor from memory, a plurality of solutions pre-stored in memory for an optimized parallelized search computation corresponding to concurrent modification of the plurality of solutions, each solution of the plurality of solutions corresponding to a unique initial candidate of a plurality of unique initial candidates and representing a plurality of values in a multi-dimensional space;
• allocating, by the processor to one or more circuits, a first corresponding solution of a first unique initial candidate from the plurality of solutions, the first corresponding solution allocated for modification by a first corresponding circuit of the one or more circuits;
• allocating, by the processor to the one or more circuits, a second corresponding solution of a second unique initial candidate from the plurality of solutions, the second corresponding solution allocated for modification by a second corresponding circuit of the one or more circuits;
• modifying, by the one or more circuits, at least one value of the first corresponding solution or the second corresponding solution of the plurality of solutions allocated to the one or more circuits to determine a plurality of modified solutions different from the plurality of solutions corresponding to the plurality of unique initial candidates retrieved from the memory;
• outputting, by the one or more circuits, a selected solution from the plurality of modified solutions, wherein the selected solution comprises:
• determining a deviation metric of plurality of modified solutions, a selected solution;
• and
• selecting, as the selected solution, a modified solution of the plurality of modified solutions based on the determined deviation metric;
• and
• causing, by the processor, a computation of one or more delivery navigation operations using the selected solution.