Prediction circuitry using a prediction table providing a skip-fetch-instruction entry

A method for controlling processing hardware circuitry and fetch hardware circuitry for fetching instructions to be processed by the processing hardware circuitry, comprising:

• performing a lookup in a prediction table based on at least part of an address of a first instruction, and
• in response to performing the lookup, identifying that the prediction table includes a skip-fetch-instruction entry corresponding to the address of the first instruction, the skip-fetch-instruction entry specifying information identifying an operation represented by at least one execute-without-fetch instruction subsequent in program order to the first instruction and the skip-fetch-instruction entry providing a target address field indicating a target address, and in response to the identifying:
• controlling the fetch hardware circuitry to skip fetching of the at least one execute-without-fetch instruction,
• controlling the processing hardware circuitry to perform the operation represented by the at least one execute-without-fetch instruction despite fetching of the at least one execute-without-fetch instruction being skipped, and
• determining the target address based on the skip-fetch-instruction entry;
• and
• resuming fetching of instructions subsequent to the first instruction, following skipping of fetching of the at least one execute-without-fetch instruction, starting from the target address.

A non-transitory computer-readable medium storing computer-readable code for fabrication of an apparatus comprising:

• fetch hardware circuitry configured to fetch instructions for processing by processing hardware circuitry, and
• prediction hardware circuitry configured to identify instructions to be fetched by the fetch hardware circuitry;
• wherein
• the prediction hardware circuitry is configured to perform a lookup in a prediction table based on at least part of an address of a first instruction, and
• in response to the lookup identifying that the prediction table includes a skip-fetch-instruction entry corresponding to the address of the first instruction, the skip-fetch-instruction entry specifying information identifying an operation represented by at least one execute-without-fetch instruction subsequent in program order to the first instruction and the skip-fetch-instruction entry providing a target address field indicating a target address, the prediction hardware circuitry is configured to:
• control the fetch hardware circuitry to skip fetching of the at least one execute-without-fetch instruction,
• control the processing hardware circuitry to perform the operation represented by the at least one execute-without-fetch instruction despite fetching of the at least one execute-without-fetch instruction being skipped, and
• determine the target address based on the skip-fetch-instruction entry;
• and
• the fetch hardware circuitry is configured to resume fetching of instructions subsequent to the first instruction, following skipping of fetching of the at least one execute-without-fetch instruction, starting from the target address.