Providing additional operations for a functional unit of a processor core

A method of operating a processor core, comprising:

• performing, by a first functional unit of the processor core configured to provide first functionality, a first set of logical operations;
• performing, by a second functional unit of the processor core configured to provide second functionality different from the first functionality, a subset of logical operations of the first set of logical operations;
• and
• receiving, from an instruction decoder, at the second functional unit rather than the first functional unit, instructions requiring the second functionality and at least one of the subset of logical operations, wherein the instructions would otherwise be routed to the first functional unit based on the instructions requiring the at least one of the subset of logical operations.

A processor core, comprising:

• first means for providing first functionality, wherein the first means for providing first functionality includes circuitry configured to perform a first set of logical operations;
• second means for providing second functionality different from the first functionality, wherein the second means for providing the second functionality includes circuitry configured to perform a subset of logical operations of the first set of logical operations;
• a data bus connecting the first means for providing the first functionality and the second means for providing the second functionality;
• and
• an instruction decoder configured to transmit instructions to the second means for providing the second functionality over the data bus, rather than the first means for providing the first functionality, based on the instructions requiring the second functionality and at least one of the subset of logical operations, wherein the instructions would otherwise be routed to the first means for providing the first functionality based on the instructions requiring the at least one of the subset of logical operations.