Apparatus and method with multiply-accumulate operation

A multiply-accumulate (MAC) computation circuit comprising:

• a bit-cell array configured to generate an analog output corresponding to a MAC operation result of an input signal, using a plurality of bit-cell groups, each comprising a plurality of output lines;
• a plurality of capacitor arrays configured to sample the analog output by converting a current value of the analog output into a voltage value, the plurality of capacitor arrays being assigned to each of the plurality of bit-cell groups;
• a plurality of first analog-to-digital conversion (ADC) circuits configured to receive the voltage value of the analog output and determine an upper part of a digital output corresponding to the analog output, the plurality of first ADC circuits being connected to the plurality of capacitor arrays;
• and
• a plurality of second ADC circuits configured to receive the voltage value of the analog output and determine a lower part of the digital output based on a reference voltage corresponding to the upper part,
• wherein the plurality of first ADC circuits are successive approximation register (SAR) ADC circuits, and the plurality of second ADC circuits are flash ADC circuits.

A multiply-accumulate (MAC) computation method comprising:

• generating an analog output corresponding to a MAC operation result of an input signal, using a bit-cell array;
• converting a current value of the analog output into a voltage value, using a capacitor array;
• receiving the voltage value of the analog output and determining an upper part of a digital output corresponding to the analog output, using a first analog-to-digital conversion (ADC) circuit;
• setting a reference voltage of a second ADC circuit based on the upper part;
• and
• receiving the voltage value of the analog output and determining a lower part of the digital output, using the second ADC circuit,
• wherein the first ADC circuit is a successive approximation register (SAR) ADC circuit, and the second ADC circuit is a flash ADC circuit.

An electronic apparatus comprising:

• a bit-cell array configured to generate an analog output corresponding to a multiply-accumulate (MAC) operation result of an input signal;
• a capacitor array configured to convert a current value of the analog output into a voltage value;
• a first analog-to-digital conversion (ADC) circuit configured to receive the voltage value of the analog output and determine high-order bits of a digital output corresponding to the analog output by comparing the analog output to one or more primary reference values determined based on a maximum value of an input signal value range;
• and
• a second ADC circuit configured to receive the voltage value of the analog output and determine low-order bits of the digital output by comparing the analog output to one or more secondary reference values determined based on the primary reference values,
• wherein the first ADC circuit is a successive approximation register (SAR) ADC circuit, and the second ADC circuit is a flash ADC circuit.