Output circuit for analog neural memory in a deep learning artificial neural network

An output circuit for generating an output from one or more arrays of non-volatile memory cells, comprising:

• a plurality of current-to-voltage converters, each of the plurality of current-to-voltage converters to generate a first voltage based on a first current received from a respective bitline coupled to one or more non-volatile memory cells of the one or more arrays storing W+ values and to generate a second voltage based on a second current received from a respective bitline coupled to one or more non-volatile memory cells of the one or more arrays storing W− values, the first voltage and the second voltage forming a differential voltage pair;
• a multiplexor for receiving a plurality of differential voltage pairs comprising the differential voltage pair generated by each of the current-to-voltage converters in the plurality of current-to-voltage converters and outputting the plurality of differential voltage pairs in a time-multiplexed manner;
• a plurality of sample-and-hold circuits, each sample-and-hold circuit configured to receive a differential voltage pair from the multiplexor and to generate a pair of differential held voltage outputs based on the differential voltage pair;
• a channel multiplexor to receive a plurality of pairs of differential held voltage outputs from the plurality of sample-and-hold circuits and to generate as an output a differential pair of the held voltage outputs in response to a control signal;
• and
• an analog-to-digital converter to convert the output from the channel multiplexor into a digital output.