Display panel

A display panel, comprising:

• an array substrate, a liquid crystal layer, and an opposite substrate disposed sequentially;
• wherein
• the opposite substrate comprises a first substrate, a black matrix layer, and a first common electrode, wherein the black matrix layer is disposed at a side of the first substrate close to the liquid crystal layer, the first common electrode is disposed at a side of the black matrix layer close to the liquid crystal layer, and the black matrix layer is provided with an opening;
• the array substrate comprises a second substrate and a pixel electrode, wherein the pixel electrode is disposed at a side of the second substrate close to the liquid crystal layer;
• the pixel electrode comprises a pixel portion, a first connection portion, and a second connection portion, wherein the second connection portion is connected to a thin film transistor, the pixel portion comprises a first trunk electrode and a first branch electrode connected to the first trunk electrode, and the first connection portion is configured to connect the second connection portion and the first branch electrode;
• and
• in a plan view of the display panel, the black matrix layer covers the first connection portion and the second connection portion, and the pixel portion is located in an area of the opening, wherein an angle formed between an extension direction of the first connection portion and an extension direction of the first branch electrode is greater than or equal to 120 degrees and less than 180 degrees, or the extension direction of the first connection portion coincides with the extension direction of the first branch electrode;
• wherein the array substrate further comprises a second common electrode, the second common electrode is disposed at a side of the second substrate close to the liquid crystal layer, the pixel electrode is disposed at a different layer from the second common electrode and disposed at a side of the second common electrode close to the liquid crystal layer, and the second common electrode is located in an area of the opening;
• the extension direction of the first connection portion coincides with the extension direction of the first branch electrode, the second connection portion comprises a via sub-portion and an extension sub-portion connecting the via sub-portion, the via sub-portion is configured to connect the thin film transistor, and the extension sub-portion is configured to connect the first connection portion;
• and
• in the plan view of the display panel, the first trunk electrode extends in a first direction, and the shortest distance from an intersection line of the extension sub-portion and the first connection portion to the second common electrode in the first direction is greater than or equal to 1.3 μm.